A novel gate over source-channel overlap dual-gate TFET with insulator pocket and lateral source contact for optimizing subthreshold characteristic

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Journal Pub Date : 2024-08-03 DOI:10.1016/j.mejo.2024.106356

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Abstract

In this work, we propose a novel hetero-junction hetero-gate-dielectric gate over source-channel overlap dual-gate TFET with an insulator pocket and a lateral source contact (IP-LSC-HJ-HGD-GoSo-DGTFET). In the IP-LSC-HJ-HGD-GoSo-DGTFET, an insulator pocket placed between channel and the right side of source is adopted to suppress the source corner effect which can cause SS to deteriorate. Therefore, an ultra-steep SS_AVER of 5.5 mV/dec is obtained within 10 orders of magnitude of I_DS. Moreover, I_OFF is improved by one order of magnitude when the vertical source contact is replaced by a lateral source contact. Finally, the I_ON, I_ON/I_OFF, V_ONSET, and g_m of IP-LSC-HJ-HGD-GoSo-DGTFET are 97 μA/μm, 2.8 × 10¹³, 0 V and 510 μS/μm through the optimization of DC performance, respectively. As for the analog/RF performance, IP-LSC-HJ-HGD-GoSo-DGTFET achieves ƒ_T of 39 GHz and GBP of 17.3 GHz, respectively. Compared with other GoSo-DGTFETs, the proposed IP-LSC-HJ-HGD-GoSo-DGTFET is a better potential candidate in the application field of ultra-low power integrated circuit.

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一种新型栅源沟道重叠双栅 TFET，具有绝缘体袋和横向源极触点，可优化阈下特性

在这项研究中，我们提出了一种新型异质结异质栅-介质栅-源极-沟道重叠双栅 TFET（IP-LSC-HJ-HGD-GoSo-DGTFET），它带有一个绝缘体口袋和一个侧面源极触点。在 IP-LSC-HJ-HGD-GoSo-DGTFET 中，沟道与源极右侧之间采用了一个绝缘体口袋，以抑制可能导致 SS 性能下降的源极拐角效应。因此，在 10 个数量级的 IDS 范围内实现了 5.5 mV/dec 的超高速 SSAVER。此外，当垂直源触点被横向源触点取代时，IOFF 提高了一个数量级。最后，通过优化直流性能，IP-LSC-HJ-HGD-GoSo-DGTFET 的 ION、ION/IOFF、VONSET 和 gm 分别为 97 μA/μm、2.8 × 1013、0 V 和 510 μS/μm。在模拟/射频性能方面，IP-LSC-HJ-HGD-GoSo-DGTFET 分别实现了 39 GHz 的 ƒT 和 17.3 GHz 的 GBP。与其他 GoSo-DGTFET 相比，所提出的 IP-LSC-HJ-HGD-GoSo-DGTFET 在超低功耗集成电路应用领域具有更好的潜力。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.