Performance enhancement of 4H-SiC superjunction trench MOSFET with extended high-K dielectric

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Journal Pub Date : 2024-08-05 DOI:10.1016/j.mejo.2024.106359
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Abstract

This paper proposes a 4H-SiC superjunction trench MOSFET with extended high-K dielectric under metal gate (EHK SJ-TMOS). The characteristics of EHK SJ-TMOS include the use of the high-K (HK) dielectric as the gate dielectric and the extension of the HK dielectric as a deep trench into the N-type drift region. The extended HK trench effectively modulates the electric field distribution in the SJ drift region, which improves the breakdown voltage (BV). The introduction of HK dielectric also assists in depleting the SJ drift region, which enables the drift region of EHK SJ-TMOS to use a higher doping concentration, thereby reducing Ron,sp. Furthermore, the application of high-K gate dielectric alleviates the high gate oxide electric field problem in conventional SiC superjunction trench MOSFETs (SiC SJ-TMOS). The simulation results demonstrate that EHK SJ-TMOS exhibits a 59.2 % reduction in Ron,sp, a 2.4 % increase in BV, and a 156.5 % improvement in the FOM (FOM = BV2/Ron,sp) compared to the SiC SJ-TMOS, indicating enhanced performance.

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采用扩展高介电质的 4H-SiC 超结沟槽 MOSFET 的性能提升
本文提出了一种金属栅极下具有扩展高 K 电介质的 4H-SiC 超结沟槽 MOSFET(EHK SJ-TMOS)。EHK SJ-TMOS 的特点包括使用高 K(HK)电介质作为栅极电介质,并将 HK 电介质作为深沟槽扩展到 N 型漂移区。延伸的 HK 沟槽有效地调节了 SJ 漂移区的电场分布,从而提高了击穿电压 (BV)。HK 电介质的引入还有助于耗尽 SJ 漂移区,使 EHK SJ-TMOS 的漂移区能够使用更高的掺杂浓度,从而降低 Ron、sp。此外,高 K 栅极电介质的应用还缓解了传统 SiC 超结沟槽 MOSFET(SiC SJ-TMOS)的高栅极氧化物电场问题。仿真结果表明,与 SiC SJ-TMOS 相比,EHK SJ-TMOS 的 Ron,sp 降低了 59.2%,BV 提高了 2.4%,FOM(FOM = BV2/Ron,sp)提高了 156.5%,性能得到了增强。
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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