Step thickness drift region automatic design of SOI LDMOS using physics-inspired constrained simulated annealing algorithm

Abstract

The introduction of the step thickness drift region (ST) technique has increased the design complexity of silicon-on-insulator (SOI) lateral double-diffused metal-oxide-semiconductor (LDMOS). This paper proposes a physics-inspired automatic optimization method for the ST structure of SOI LDMOS using constrained simulated annealing algorithm. Since breakdown voltage (BV) and specific on-resistance (R_on,sp) need to be optimized simultaneously, an optimization function based on Baliga's Figure of Merit (BFOM) is introduced. Besides, constraints are introduced to ensure that BV is greater than the initial BV and R_on,sp is less than the initial R_on,sp. Results demonstrate that the BFOM values increase by an average of 134.9 %, 163.6 %, and 113.8 % when the breakdown occurs at the N⁺N junction, PN junction, and in-the-body after optimizing the ST structure, respectively. Besides, introducing constraints during the automatic design process allows for the simultaneous optimization of both the BV and R_on,sp. Furthermore, the proposed method is also efficient, with 86 % of the optimization design processes completed within 18 seconds.