An Analog Integrated Multiloop LDO: From Analysis to Design

Abstract

This paper introduces a multiloop stabilized low-dropout regulator with a DC power supply rejection ratio of 85 dB and a phase margin of 80°. It is suitable for low-power, low-voltage and area-efficient applications since it consumes less than 100 μA. The dropout voltage is only 400 mV and the power supply rails are 1 V. Furthermore, a full mathematical analysis is conducted for stability and noise before the circuit verification. To confirm the proper operation of the implementation process, voltage and temperature corner variation simulations are extracted. The proposed regulator is designed and verified utilizing the Cadence IC Suite in a TSMC 90 nm CMOS process.