Research on single event effects and hardening design of LDMOS transistors

Abstract

In this paper, an N-type Lateral Diffused Metal Oxide Semiconductor (LDMOS) device was designed using a heavily doped P+ well and drain N-type buffer layer structure in the BCD process. The hardened mechanism of heavily doped P+ well and drain N-type buffer layer structures was simulated and analyzed using a TCAD device simulator. To verify the anti-SEE performance of the LDMOS, the irradiation test was conducted using Ta ion (LET = 79.2 MeV·cm⁻² mg⁻¹). The results show that increasing P+ well doping concentration and using buffer layer structure can increase the single event burnout (SEB) voltage of high-voltage LDMOS devices. SEB did not occur within the full operation voltage range.