GNN-SP: Fast S-Parameter Estimation of Chiplet Interconnect via Graph Neural Network

Abstract

A chiplet-based heterogeneous integrated system design has emerged as a new trend in advanced packaging. However, the high density and complexity of high-speed interconnects between chiplets introduce significant signal integrity (SI) challenges. Rapid and accurate assessment of SI during the design stage is critical to ensure the functionality and performance of chiplet-based systems. Traditional numerical methods for evaluating SI, such as the method of moments (MoM), face challenges due to their substantial demands on computing time and hardware resources. This work presents GNN-SP, a novel graph neural network (GNN)-based method for rapid S-parameter estimation of chiplet interconnects, as well as an open dataset for chiplet interconnect SI based on the Universal Chiplet Interconnect Express (UCIe) standard. GNN is capable of capturing different combinations of local interconnect patterns through message passing, and in GNN-SP, global information is encoded into graph nodes to be incorporated into the node aggregation process. Therefore, the GNN model is able to learn both global and intricate local information of complex interconnects. Compared with convolutional neural networks (CNNs) and multilayer perceptron (MLP)-based methods for predicting the magnitude and phase of S-parameters, GNN-SP reduces the average relative error from 70% to 90% and achieves a speedup of $1.3{\times }$ – $9.97{\times }$ . Compared with the commercial Agilent advanced design system (ADS) Momentum simulator based on the MoM, GNN-SP achieves a speedup of 22 $099{\times }$ with an average relative error below 1.93% for insertion/return loss and an average relative error below 3.31% for crosstalk.