Challenges and Technologies of Frontside Via-Last Active-Interposer Processes on Low-k Material for 3-D Chiplet

Abstract

The three-dimensional chiplet technology based on through-silicon via (TSV) active interposer is an effective way to continue increasing integration reducing power and improving performance as Moore’s law slows down. The TSV active interposer not only provides paths for die-to-die interconnections but also integrates logic functions. In this study, an active interposer fabrication technique for integrated TSVs was developed. The active interposer was successfully fabricated by the frontside via-last technology. However, due to the low-k material on the top side of the wafer, the process of the active interposer faces many challenges, including the TSV etching, the TSV cleaning, and the scribing of the low-k wafer. This work proposed the double-step protection method to avoid the overetching of TSV due to the porous structure of the low-k material. Then, the 350 °C baking for 1 h after the wafer cleaning method was proposed to avoid short-circuiting due to the water absorption characteristics of the low-k material. Besides, the blade saw followed by laser grooving method was proposed to avoid chipping and splattering of the wafer due to the low mechanical strength of the low-k material. Finally, the TSV active interposer was fabricated to conform with the design requirements and to satisfy the application of the 3-D chiplet. The dimension of the active interposer was $22\times 20$ mm. The main connection structures of the active interposer were fabricated by the back end of line (BEOL). The frontside contained the TSVs ( $10\times 100~\mu $ m), three metal layers, and microbumps with $26.2~\mu $ m diameter and $18.8~\mu $ m height. The backside contained one metal layer and C4 bumps with $77.6~\mu $ m diameter and $77.3~\mu $ m height. The survival rate of the sample is about 89% after the 200 cycles thermal cycling test (TCT), from −40 °C to 125 °C.