A 62.5 kHz-BW 92 dB-SNDR noise-shaping SAR ADC with NS-CAL method

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Journal Pub Date : 2024-09-05 DOI:10.1016/j.mejo.2024.106401

Jianzheng Li , Yuchen Zhao , Weimin Hu , Jinghan Yao , Ziwei Liu , Yajie Qin

引用次数: 0

Abstract

DAC mismatch is a significant error in NS-SAR ADCs, as it introduces essentially nonlinear behavior and limits the number of bits in the DAC array. In this paper, we propose a novel foreground digital calibration method for NS-SAR ADCs. This method, combined with noise shaping technique, improves calibration accuracy and eliminates the impact of error accumulation on high-bit weights. Thus, it increases the number of bits in the DAC array in NS-SAR ADCs, and decreases the noise floor caused by quantization error. We implemented this design using a 110-nm CMOS process. As a result, post-layout simulation shows 92 dB SNDR and 108 dB SFDR under × 16 OSR and 1.5 V supply. Compared with conventional foreground calibration method, the SNDR increases from 81 dB to 92 dB and the SFDR increases from 84 dB to 108 dB with a power consumption of 40 μW, resulting in a FoMs of 182 dB and a FoMw of 15.3 fJ/conversion-step, respectively.

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采用 NS-CAL 方法的 62.5 kHz-BW 92 dB-SNDR 噪声整形 SAR ADC

DAC 不匹配是 NS-SAR ADC 中的一个重大误差，因为它会引入本质上的非线性行为，并限制 DAC 阵列的位数。在本文中，我们为 NS-SAR ADC 提出了一种新颖的前景数字校准方法。该方法与噪声整形技术相结合，提高了校准精度，并消除了误差累积对高位权重的影响。因此，它增加了 NS-SAR ADC 中 DAC 阵列的位数，并降低了量化误差引起的本底噪声。我们采用 110 纳米 CMOS 工艺实现了这一设计。结果，布局后仿真显示，在 × 16 OSR 和 1.5 V 电源条件下，SNDR 为 92 dB，SFDR 为 108 dB。与传统的前景校准方法相比，SNDR 从 81 dB 提高到 92 dB，SFDR 从 84 dB 提高到 108 dB，功耗为 40 μW，FoMs 为 182 dB，FoMw 为 15.3 fJ/转换步。

本文章由计算机程序翻译，如有差异，请以英文原文为准。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.

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