The Analytical Model of Hotspot Temperature and the Effects of Different Factors in 3-D Integration

Abstract

The three-dimensional integration technology is an effective solution of extending Moore’s law, with better performance and higher density. However, the temperature rise caused by hot spots in 3-D integration will be more prominent. By extracting the equivalent thermal conductivity of the microbump layer and the chip with TSVs, the equivalent analytical model for detailed 3-D integration structure is proposed in this article. The accuracy of equivalence is verified using finite element simulation, and the model is used to calculate the thermal resistance and to predict the maximum temperature of the hot spot. In 3-D integration, the second conduction path can significantly reduce the temperature of the hot spot. A new analytical solution is proposed in this article for calculating thermal resistance and predicting the maximum temperature of the hot spot in 3-D integration. The results demonstrate that the thermal resistance network model proposed can precisely predict the temperature rise of the hot spot. For hot spots with different sizes, the error between simulation and network model is merely within $2~^{\circ }$ C. The effects of different factors on the hotspot temperature rise in 3-D integration is investigated. As the chip material, diamond can significantly reduce the hotspot temperature. Furthermore, both the chip thickness and the thermal conductivity of microbump layer have effect on the temperature of hot spot with different sizes. For cases with large-sized hot spot, to decrease the hotspot temperature, smaller microbump and greater chip thickness are advised in packaging.