Asymmetric Trench SiC MOSFET With Integrated Channel Accumulation Diode for Enhanced Reverse Conduction and Switching Characteristics

IF 1.9 3区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Journal Pub Date : 2024-10-09 DOI:10.1016/j.mejo.2024.106436
Sheng Gao , Xianfeng Zhang , Qi Wang , Shengqi Yu , Yang Zuo , Hongsheng Zhang , Yi Huang
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Abstract

A novel asymmetric trench Silicon Carbide Metal Oxide Semiconductor Field Effect Transistor (SiC MOSFET), featuring an integrated channel accumulation diode (CAD-MOS), has been proposed and investigated through numerical simulation. This innovative design aims to mitigate switching losses and eliminate the bipolar degradation of the body diode. The current spreading layer (CSL) channel, strategically positioned in the centre of the dummy gate, offers a low-barrier reverse conduction path. This represents a substantial advancement over the traditional PN body diode, significantly reducing the reverse conduction voltage drop from 2.84 V in the PN body diode to a mere 1.39 V in the CAD-MOS. Meanwhile, the reverse recovery charge of the CAD-MOS is reduced to 0.95 μC/cm2, and the peak reverse recovery current stands at 45 A/cm2. Compared to conventional asymmetrical trench SiC MOSFET (CON-MOS), the CAD-MOS exhibits a 68.1% reduction in reverse recovery charge and a 63.4% decrease in peak reverse recovery current. The split-gate design also reduces the device gate to source capacitance (CGS), resulting in a 17.4% reduction in total switching losses to 3.64 mJ/cm2. CAD-MOS also exhibits a reduced gate turn-on charge and demonstrates an enhancement in high-frequency figure of merit (HF-FOM) by 8.1%.
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集成沟道累积二极管的非对称沟道碳化硅 MOSFET,可增强反向传导和开关特性
我们提出了一种新型非对称沟道碳化硅金属氧化物半导体场效应晶体管(SiC MOSFET),其特点是集成了沟道积放二极管(CAD-MOS),并通过数值模拟进行了研究。这种创新设计旨在减少开关损耗,消除体二极管的双极退化。电流扩散层 (CSL) 沟道战略性地设置在假栅极中心,提供了一条低势垒反向传导路径。与传统的 PN 体二极管相比,CAD-MOS 的反向传导压降从 PN 体二极管的 2.84 V 显著降至 1.39 V。同时,CAD-MOS 的反向恢复电荷降至 0.95 μC/cm2,反向恢复电流峰值为 45 A/cm2。与传统的非对称沟道 SiC MOSFET(CON-MOS)相比,CAD-MOS 的反向恢复电荷减少了 68.1%,反向恢复峰值电流减少了 63.4%。分裂栅极设计还降低了器件栅极到源极电容 (CGS),从而将总开关损耗降低了 17.4%,达到 3.64 mJ/cm2。CAD-MOS 还降低了栅极导通电荷,并将高频性能指标 (HF-FOM) 提高了 8.1%。
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来源期刊
Microelectronics Journal
Microelectronics Journal 工程技术-工程:电子与电气
CiteScore
4.00
自引率
27.30%
发文量
222
审稿时长
43 days
期刊介绍: Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.
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