Smart-CX – Method of extraction of parasitic capacitances in ICs

Abstract

This paper proposes a novel rule-based parasitic capacitance extraction methodology, integrated into Smart-CX, to enhance the accuracy of SPICE simulations and physical verification of ICs. This methodology is crucial during the microchip design phase, particularly in preparation for fabrication on mature to advanced process nodes. The proposed enhanced analytical method addresses the accuracy/time tradeoffs between numerical and analytical extraction techniques. This study validates the accuracy of the methodology by comparison of the extracted parasitic parameters with foundry-provided 2D-models. The parasitic capacitances that are extracted within this method include: area capacitances $\left(Ca\right)$, coupling capacitances ($Cc)$, including via-to-via capacitances $\left(Cmv\right)$, contact-to-gate capacitances $\left(Cmg\right)$, contact-to-active capacitances ($Cmc)$ and fringe type capacitances with the top $\left(Cft\right)$ and bottom $\left(Cfb\right)$ conductive layers.