Kent Edrian Lozada;Dong-Jin Chang;Dong-Ryeol Oh;Min-Jae Seo;Seung-Tak Ryu
{"title":"SAR-Assisted Energy-Efficient Hybrid ADCs","authors":"Kent Edrian Lozada;Dong-Jin Chang;Dong-Ryeol Oh;Min-Jae Seo;Seung-Tak Ryu","doi":"10.1109/OJSSCS.2024.3472000","DOIUrl":null,"url":null,"abstract":"The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conversion in the SAR ADC negates the need for complex residue extraction circuits. This crucial feature has inspired numerous SAR-assisted architectural variations, employed in a range of applications from high resolution to high speed. This article introduces several energy-efficient hybrid ADC architectures that incorporate SAR ADCs as their sub blocks, including the following: SAR-assisted subranging SAR, which saves DAC switching power and can detect skew errors for time-interleaved ADCs; SAR-flash hybrid for energy-efficient high-speed conversion; SAR-assisted dual-residue pipelined ADC, which eliminates the stringent requirement for residue gain accuracy; and SAR-assisted delta–sigma modulator (DSM) with digital-domain noise coupling, which reduces the number of required analog integrators.","PeriodicalId":100633,"journal":{"name":"IEEE Open Journal of the Solid-State Circuits Society","volume":"4 ","pages":"163-175"},"PeriodicalIF":0.0000,"publicationDate":"2024-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10702510","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Open Journal of the Solid-State Circuits Society","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10702510/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
The distinct advantages of low power consumption and hardware compactness make SAR ADCs especially appealing in scaled CMOS technologies, garnering significant attention. The residue left on the capacitor digital-to-analog converter (CDAC) after conversion in the SAR ADC negates the need for complex residue extraction circuits. This crucial feature has inspired numerous SAR-assisted architectural variations, employed in a range of applications from high resolution to high speed. This article introduces several energy-efficient hybrid ADC architectures that incorporate SAR ADCs as their sub blocks, including the following: SAR-assisted subranging SAR, which saves DAC switching power and can detect skew errors for time-interleaved ADCs; SAR-flash hybrid for energy-efficient high-speed conversion; SAR-assisted dual-residue pipelined ADC, which eliminates the stringent requirement for residue gain accuracy; and SAR-assisted delta–sigma modulator (DSM) with digital-domain noise coupling, which reduces the number of required analog integrators.