Study on single-event burnout hardening with reduction of hole current density by top polysilicon diode of SOI LDMOS based on TCAD simulations

Abstract

In this paper, a single-event burnout (SEB)-hardened design for silicon-on-insulator lateral double-diffused MOSFET (SOI LDMOS) with a top polysilicon PN-junction diode (PN-LDMOS) is presented. By analyzing the hole current density of the device at different time points after a heavy-ion event, it is found that the introduced top polysilicon diode structure can reduce the hole current flowing to the source remarkably at a certain time. Thus, the voltage drop between the emitter and base of the parasitic NPN bipolar junction transistor (BJT) inherent in the device structure is reduced, and the deep p+ structure provides a low resistance path for the holes. The combined effect of these two structures effectively suppresses the turn-on of parasitic BJT and significantly reduces the risk of SEB occurrence. Compared to the traditional LDMOS (C-LDMOS), at a LET of 0.2 pC/μm, the SEB trigger voltage (V_SEB) of PN-LDMOS is improved from 129 V to 200 V, and the safe operating area (SOA) ratio (η) is increased from 58.8 % to 80 %. And the combination of polysilicon diode and field plates also optimizes the surface electric field distribution, increasing the breakdown voltage from 219.4 V to 249.7 V.