Nayeon Kim , Jiae Jeong , Jae Woo Lee , Jiyong Woo
{"title":"Unraveling the role of post-annealing in IGZO transistor for memory applications","authors":"Nayeon Kim , Jiae Jeong , Jae Woo Lee , Jiyong Woo","doi":"10.1016/j.mee.2025.112322","DOIUrl":null,"url":null,"abstract":"<div><div>We demonstrate that post-annealing techniques are important for achieving the transfer characteristics of indium‑gallium‑zinc oxide (IGZO) transistors and identify that their role depends on the sputter-deposited IGZO film conditions. The as-fabricated transistor with a thin IGZO channel, HfO<sub>2</sub> gate dielectric, and Mo gate electrode exhibits a constant drain current (I<sub>DS</sub>) over gate voltage (V<sub>GS</sub>). Although the oxygen (O<sub>2</sub>) plasma gas rate is adjusted from 0.2 to 1 sccm with an argon gas rate of 30 sccm during IGZO deposition, the I<sub>DS</sub> level was reduced by a factor of 10<sup>4</sup>. Notably, V<sub>GS</sub>-controlled transfer behavior of the transistors only starts after post-annealing is performed at temperatures above 300 °C, regardless of which IGZO channel properties are used. More specifically, since oxygen vacancies (V<sub>O</sub>s) serve as carriers in the IGZO, annealing in different O<sub>2</sub> gas or air environments to generate or reduce the number of V<sub>O</sub>s is found to be optimal for the V<sub>O</sub>-rich or V<sub>O</sub>-poor channels, respectively. In this study, we reveal that oxidation annealing appears to be a more effective way for achieving improved gate controllability (e.g., subthreshold swing). Accordingly, we further analyze how the V<sub>O</sub>s in the IGZO are involved in switching by examining the effect of annealing temperature and gate dielectric materials on the transfer curve. These results indicate that V<sub>O</sub>s in the bulk need to be annihilated to lower the off-state I<sub>DS</sub>, while a sufficient number of V<sub>O</sub>s near the channel and gate dielectric interface should be ensured to responded by V<sub>GS</sub> for rapid switching.</div></div>","PeriodicalId":18557,"journal":{"name":"Microelectronic Engineering","volume":"298 ","pages":"Article 112322"},"PeriodicalIF":2.6000,"publicationDate":"2025-01-19","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronic Engineering","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0167931725000115","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
We demonstrate that post-annealing techniques are important for achieving the transfer characteristics of indium‑gallium‑zinc oxide (IGZO) transistors and identify that their role depends on the sputter-deposited IGZO film conditions. The as-fabricated transistor with a thin IGZO channel, HfO2 gate dielectric, and Mo gate electrode exhibits a constant drain current (IDS) over gate voltage (VGS). Although the oxygen (O2) plasma gas rate is adjusted from 0.2 to 1 sccm with an argon gas rate of 30 sccm during IGZO deposition, the IDS level was reduced by a factor of 104. Notably, VGS-controlled transfer behavior of the transistors only starts after post-annealing is performed at temperatures above 300 °C, regardless of which IGZO channel properties are used. More specifically, since oxygen vacancies (VOs) serve as carriers in the IGZO, annealing in different O2 gas or air environments to generate or reduce the number of VOs is found to be optimal for the VO-rich or VO-poor channels, respectively. In this study, we reveal that oxidation annealing appears to be a more effective way for achieving improved gate controllability (e.g., subthreshold swing). Accordingly, we further analyze how the VOs in the IGZO are involved in switching by examining the effect of annealing temperature and gate dielectric materials on the transfer curve. These results indicate that VOs in the bulk need to be annihilated to lower the off-state IDS, while a sufficient number of VOs near the channel and gate dielectric interface should be ensured to responded by VGS for rapid switching.
期刊介绍:
Microelectronic Engineering is the premier nanoprocessing, and nanotechnology journal focusing on fabrication of electronic, photonic, bioelectronic, electromechanic and fluidic devices and systems, and their applications in the broad areas of electronics, photonics, energy, life sciences, and environment. It covers also the expanding interdisciplinary field of "more than Moore" and "beyond Moore" integrated nanoelectronics / photonics and micro-/nano-/bio-systems. Through its unique mixture of peer-reviewed articles, reviews, accelerated publications, short and Technical notes, and the latest research news on key developments, Microelectronic Engineering provides comprehensive coverage of this exciting, interdisciplinary and dynamic new field for researchers in academia and professionals in industry.