V.C.P. Silva , A.R. Ribeiro , J.A. Martino , A. Veloso , N. Horiguchi , P.G.D. Agopian
{"title":"Analog behavior of V-FET operating in forward and reverse mode","authors":"V.C.P. Silva , A.R. Ribeiro , J.A. Martino , A. Veloso , N. Horiguchi , P.G.D. Agopian","doi":"10.1016/j.sse.2025.109073","DOIUrl":null,"url":null,"abstract":"<div><div>This work investigates the analog parameters of p-type Vertical Field-Effect Nanowire Transistors (V-FETs) built on a Silicon-On-Insulator (SOI) wafer, focusing on variations in channel (nanowire) diameter (CD) and two different operational modes: forward (source as the bottom electrode) and reverse (source as the top electrode). When CD decreases from 40 to 20 nm in forward mode, the subthreshold swing (SS) improves from 93 to 76 mV/dec, the Drain-Induced Barrier Lowering (DIBL) also improves from 138 to 43 mV/V and the intrinsic voltage gain (A<sub>V</sub>) increases from 19 to 34 dB. The reduction in CD enhances electrostatic control of the gate over the channel, leading to improved transistor characteristics. A significant impact of the access resistance at the top electrode is observed in forward mode. While forward mode presents an improvement in DIBL, V<sub>EA</sub> and A<sub>V</sub>, in the reverse mode shows better gm<sub>sat</sub>, SS<sub>sat</sub> and f<sub>T</sub>. Additionally, the trade-off analysis between intrinsic voltage gain and unity gain frequency (f<sub>T</sub>) resulted in an optimal point at strong version for the inversion coefficient (IC) = 63, A<sub>V</sub> = 28 dB and f<sub>T</sub> = 2.6 GHz in forward mode, and for IC = 34, AV = 20 dB and f<sub>T</sub> = 3.7 GHz in reverse mode.</div></div>","PeriodicalId":21909,"journal":{"name":"Solid-state Electronics","volume":"225 ","pages":"Article 109073"},"PeriodicalIF":1.4000,"publicationDate":"2025-01-22","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Solid-state Electronics","FirstCategoryId":"101","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0038110125000188","RegionNum":4,"RegionCategory":"物理与天体物理","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 0
Abstract
This work investigates the analog parameters of p-type Vertical Field-Effect Nanowire Transistors (V-FETs) built on a Silicon-On-Insulator (SOI) wafer, focusing on variations in channel (nanowire) diameter (CD) and two different operational modes: forward (source as the bottom electrode) and reverse (source as the top electrode). When CD decreases from 40 to 20 nm in forward mode, the subthreshold swing (SS) improves from 93 to 76 mV/dec, the Drain-Induced Barrier Lowering (DIBL) also improves from 138 to 43 mV/V and the intrinsic voltage gain (AV) increases from 19 to 34 dB. The reduction in CD enhances electrostatic control of the gate over the channel, leading to improved transistor characteristics. A significant impact of the access resistance at the top electrode is observed in forward mode. While forward mode presents an improvement in DIBL, VEA and AV, in the reverse mode shows better gmsat, SSsat and fT. Additionally, the trade-off analysis between intrinsic voltage gain and unity gain frequency (fT) resulted in an optimal point at strong version for the inversion coefficient (IC) = 63, AV = 28 dB and fT = 2.6 GHz in forward mode, and for IC = 34, AV = 20 dB and fT = 3.7 GHz in reverse mode.
期刊介绍:
It is the aim of this journal to bring together in one publication outstanding papers reporting new and original work in the following areas: (1) applications of solid-state physics and technology to electronics and optoelectronics, including theory and device design; (2) optical, electrical, morphological characterization techniques and parameter extraction of devices; (3) fabrication of semiconductor devices, and also device-related materials growth, measurement and evaluation; (4) the physics and modeling of submicron and nanoscale microelectronic and optoelectronic devices, including processing, measurement, and performance evaluation; (5) applications of numerical methods to the modeling and simulation of solid-state devices and processes; and (6) nanoscale electronic and optoelectronic devices, photovoltaics, sensors, and MEMS based on semiconductor and alternative electronic materials; (7) synthesis and electrooptical properties of materials for novel devices.