ECRAAL: a high-performance multiplier design by efficient charge recovery asynchronous adiabatic logic

Abstract

Power consumption is one of the most important factors in modern digital signal processor (DSP) systems. A number of measures for minimizing power consumption, such as reducing supply voltage, switching activity, and capacitance, have been incorporated into the digital design of complementary metal oxide semiconductors (CMOS). However, these strategies don't work with the current CMOS design. As a result, this study concentrated on adiabatic logic, which has proven to be an outstanding way for developing low-power digital circuits. Adiabatic logic circuits return power to their source rather than release power as heat. So, in this research, novel and efficient charge recovery asynchronous adiabatic logic (ECRAAL)-based logic gates are developed to design a high-performance multiplier for high-speed digital circuits. The proposed adiabatic logic-based multiplier is designed using the Tanner EDA tool, and various performance metrics are used to assess the proposed multiplier's efficacy. The results analyzed show that the proposed 16-bit multiplier has a maximum propagation delay that is 38.46% and 16.46% less than Transmission Gate (TG) CMOS and Transmission-gate based Full Adder (TFA) designs, respectively.