An Ultra-Low-Power Amplifier-Less Potentiostat Design Based on Digital Regulation Loop

Muhammad Abrar Akram;Aida Aberra;Soon-Jae Kweon;Sohmyung Ha
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Abstract

This paper presents a new potentiostat circuit architecture for interfaces with amperometric electrochemical biosensors. The proposed architecture, which is based on a digital low-dropout regulator (DLDO) structure, successfully eliminates the need for transimpedance amplifier (TIA), control amplifier, and other passive elements unlike other typical potentiostat topologies. It can regulate the required electrode voltages and measure the sensor currents ($\textit{I}_{\textit{SENSE}}$) at the same time by using a simple implementation with clocked comparators, digital loop filters, and current-steering DACs. Three different configurations of the proposed potentiostat are discussed including single-side regulated (SSR) potentiostat, dual-side regulated (DSR) potentiostat, and differential sensing DSR potentiostat with a background working electrode. These proposed potentiostats were designed and fabricated in a 180 nm complementary metal-oxide semiconductor (CMOS) process, occupying an active silicon areas of 0.0645 mm${}^{2}$, 0.1653 mm${}^{2}$, and 0.266 mm${}^{2}$, respectively. Validation results demonstrate that the proposed potentiostats operate on a wide sampling frequency range from 100 Hz to 100 MHz and supply voltage range from 1 V to 1.8 V. The proposed DSR potentiostat achieves a minimal power consumption of 3.7 nW over the entire dynamic range of 129.5 dB.
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一种基于数字调节回路的超低功率无放大器恒电位器设计。
本文提出了一种用于安培电化学生物传感器接口的新型恒电位电路结构。所提出的架构基于数字低差调节器(DLDO)结构,与其他典型的恒电位器拓扑结构不同,它成功地消除了对跨阻放大器(TIA)、控制放大器和其他无源元件的需求。它可以调节所需的电极电压和测量传感器电流(ISENSE)在同一时间通过使用一个简单的实现与时钟比较器,数字环路滤波器和电流转向dac。本文讨论了三种不同配置的恒电位器,包括单侧调节(SSR)恒电位器、双侧调节(DSR)恒电位器和带有背景工作电极的差分传感DSR恒电位器。这些恒电位器是在180 nm CMOS工艺中设计和制造的,分别占据0.0645 mm2, 0.1653 mm2和0.266 mm2的有源硅面积。验证结果表明,所设计的恒电位器工作在100hz ~ 100mhz的宽采样频率范围内,电源电压范围为1v ~ 1.8 V。所提出的DSR恒电位器在129.5 dB的整个动态范围内实现了3.7 nW的最小功耗。
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