Vertical scale-down of Cu/low-k interconnect development for BEOL reliability improvement of 12nm DRAM

Abstract

The effect of vertical scale-down of Cu interconnects on power consumption efficiency and back-end of the line (BEOL) reliability was investigated in 12nm DDR5 DRAM with four metal layers. The hydrostatic stress gradient, which drives stress migration (SM) failure was calculated using the finite element method, and it decreased in the scaled interconnect, thus leading to an improvement in the SM reliability. The time-dependent dielectric breakdown (TDDB) lifetime was also enhanced by the decrease in electric field between scaled Cu interconnects, which was demonstrated by both of the simulation and measurement. Although scaled interconnect could deteriorate the EM lifetime due to the increase in grain boundary, controlling the barrier metal thickness and utilizing advanced capping layer have compensated for the electro-migration (EM) deterioration. As a result, 12nm DDR5 DRAM meets 125°C BEOL reliability criteria while implementing low power through vertical scale-down of Cu interconnect.