A deep trench-type SiC MOSFET integrated with Schottky diode for enhanced oxide reliability and switching performances

IF 1.9 3区工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Microelectronics Journal Pub Date : 2025-03-07 DOI:10.1016/j.mejo.2025.106639

Liang Tian, Qingchun Zhang

{"title":"A deep trench-type SiC MOSFET integrated with Schottky diode for enhanced oxide reliability and switching performances","authors":"Liang Tian, Qingchun Zhang","doi":"10.1016/j.mejo.2025.106639","DOIUrl":null,"url":null,"abstract":"<div><div>This paper presents a novel deep trench-type SiC MOSFET integrated with Schottky diodes (DT-JMOS) designed to improve oxide reliability and switching performances. In contrast to conventional SiC trench MOSFET with Schottky diodes (CT-JMOS), the DT-JMOS utilizes a narrower JFET region and a P-bot structure, resulting in superior electric field reductions in gate oxide layer to improve reliability. The unique structure also enables double-channel operation and deeper embedded Schottky contacts, significantly enhancing the current conduction capabilities in both the first and third quadrants. Furthermore, simulation results indicate that the DT-JMOS achieves a 97.6 % decrease in gate-to-drain capacitance (Cgd), leading to a 67.5 % improvement in gate-to-drain charge (Qgd), and eventually resulting in reductions by factors of 3.2 and 3.5 for figure of merit Qgd × Ron,sp and total switching losses (Etotal), respectively. These attributes suggest that the DT-JMOS is more suitable for high-voltage and high-frequency applications.</div></div>","PeriodicalId":49818,"journal":{"name":"Microelectronics Journal","volume":"159 ","pages":"Article 106639"},"PeriodicalIF":1.9000,"publicationDate":"2025-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Microelectronics Journal","FirstCategoryId":"5","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S1879239125000888","RegionNum":3,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}

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Abstract

This paper presents a novel deep trench-type SiC MOSFET integrated with Schottky diodes (DT-JMOS) designed to improve oxide reliability and switching performances. In contrast to conventional SiC trench MOSFET with Schottky diodes (CT-JMOS), the DT-JMOS utilizes a narrower JFET region and a P-bot structure, resulting in superior electric field reductions in gate oxide layer to improve reliability. The unique structure also enables double-channel operation and deeper embedded Schottky contacts, significantly enhancing the current conduction capabilities in both the first and third quadrants. Furthermore, simulation results indicate that the DT-JMOS achieves a 97.6 % decrease in gate-to-drain capacitance (C_gd), leading to a 67.5 % improvement in gate-to-drain charge (Q_gd), and eventually resulting in reductions by factors of 3.2 and 3.5 for figure of merit Q_gd × R_on,sp and total switching losses (E_total), respectively. These attributes suggest that the DT-JMOS is more suitable for high-voltage and high-frequency applications.

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与肖特基二极管集成的深沟槽型SiC MOSFET，可增强氧化物可靠性和开关性能

本文提出了一种集成肖特基二极管（DT-JMOS）的新型深沟槽型SiC MOSFET，旨在提高氧化物可靠性和开关性能。与传统的具有肖特基二极管的SiC沟槽MOSFET （CT-JMOS）相比，DT-JMOS利用更窄的JFET区域和P-bot结构，导致栅极氧化层的优越电场减小，从而提高可靠性。独特的结构还支持双通道操作和更深的嵌入式肖特基触点，显着提高了第一和第三象限的电流传导能力。此外，仿真结果表明，DT-JMOS的栅极漏极电容（Cgd）降低了97.6%，栅极漏极电荷（Qgd）提高了67.5%，最终使品质因数Qgd × Ron、sp和总开关损耗（Etotal）分别降低了3.2和3.5倍。这些特性表明DT-JMOS更适合高压和高频应用。

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来源期刊

Microelectronics Journal 工程技术-工程：电子与电气

CiteScore

4.00

自引率

27.30%

发文量

222

审稿时长

43 days

期刊介绍： Published since 1969, the Microelectronics Journal is an international forum for the dissemination of research and applications of microelectronic systems, circuits, and emerging technologies. Papers published in the Microelectronics Journal have undergone peer review to ensure originality, relevance, and timeliness. The journal thus provides a worldwide, regular, and comprehensive update on microelectronic circuits and systems. The Microelectronics Journal invites papers describing significant research and applications in all of the areas listed below. Comprehensive review/survey papers covering recent developments will also be considered. The Microelectronics Journal covers circuits and systems. This topic includes but is not limited to: Analog, digital, mixed, and RF circuits and related design methodologies; Logic, architectural, and system level synthesis; Testing, design for testability, built-in self-test; Area, power, and thermal analysis and design; Mixed-domain simulation and design; Embedded systems; Non-von Neumann computing and related technologies and circuits; Design and test of high complexity systems integration; SoC, NoC, SIP, and NIP design and test; 3-D integration design and analysis; Emerging device technologies and circuits, such as FinFETs, SETs, spintronics, SFQ, MTJ, etc. Application aspects such as signal and image processing including circuits for cryptography, sensors, and actuators including sensor networks, reliability and quality issues, and economic models are also welcome.