Ultracompact On-Chip Branch Line Coupler Based on Through-Silicon Via Technology

IF 3 3区 工程技术 Q2 ENGINEERING, ELECTRICAL & ELECTRONIC IEEE Transactions on Components, Packaging and Manufacturing Technology Pub Date : 2025-01-24 DOI:10.1109/TCPMT.2025.3533615
Yue Deng;Fengjuan Wang;Xiangkun Yin;Sa Xiao;Yuan Yang;Ningmei Yu
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Abstract

A compact branch line coupler with lumped elements on silicon substrate is realized by employing through-silicon via (TSV) technology, in which the lumped elements adopt high-density, high-Q 3-D solenoid inductors, and double-layer interdigital capacitors, and the proposed coupler is fabricated and measured. The results show that the return loss of the coupler is less than -19.7 dB, the isolation is less than -15.2 dB at 4.7–5.3 GHz, and the phase imbalance within the operating frequency range is within ±1.2°. In addition, the size of the branch line coupler is only $1.2\times 1.36$ mm2 ( $0.069\times 0.078~\lambda _{\text {g}}^{2}$ ).
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基于硅通孔技术的超紧凑片上支路耦合器
通过采用硅通孔(TSV)技术,在硅衬底上实现了一种带有叠加元件的紧凑型分支线耦合器,其中叠加元件采用了高密度、高Q值的三维螺线管电感器和双层数字间电容器,并对所提出的耦合器进行了制造和测量。结果表明,耦合器的回波损耗小于 -19.7 dB,在 4.7-5.3 GHz 频率下的隔离度小于 -15.2 dB,工作频率范围内的相位不平衡度在±1.2°以内。此外,支线耦合器的尺寸仅为 1.2 美元乘以 1.36$ mm2 (0.069 美元乘以 0.078~\lambda _{text {g}}^{2}$ )。
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来源期刊
IEEE Transactions on Components, Packaging and Manufacturing Technology
IEEE Transactions on Components, Packaging and Manufacturing Technology ENGINEERING, MANUFACTURING-ENGINEERING, ELECTRICAL & ELECTRONIC
CiteScore
4.70
自引率
13.60%
发文量
203
审稿时长
3 months
期刊介绍: IEEE Transactions on Components, Packaging, and Manufacturing Technology publishes research and application articles on modeling, design, building blocks, technical infrastructure, and analysis underpinning electronic, photonic and MEMS packaging, in addition to new developments in passive components, electrical contacts and connectors, thermal management, and device reliability; as well as the manufacture of electronics parts and assemblies, with broad coverage of design, factory modeling, assembly methods, quality, product robustness, and design-for-environment.
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