Fabrication-Induced Warpage Characterization Analysis of Micro-LED Fan-Out Packaging

Abstract

The advancement of light-emitting diode (LED) packaging technology has been driven by the increasing demand for high-performing and compact lighting solutions. Traditional packaging methods, such as chip-on-board technology and surface-mount technology, face challenges in meeting the demands for high input/output density and effective thermal management. This scenario has led to the adoption of advanced packaging technologies, including wafer-level packaging (WLP) and fan-out (FO) technology, which offer advantages such as improved surface flatness, reduced dielectric loss, and cost-effectiveness. This study presents a novel FO-LED architecture with a redistribution layer (RDL)-first design to achieve high density and thin form factors. A 3-D finite element analysis (FEA) model that incorporates equivalent material properties for the RDL and Cu pillar bumps is developed to analyze the warpage behavior induced during the FO-LED assembly fabrication process. The model’s validity is confirmed by comparing simulation results with experimental measurements obtained at various stages of FO-LED fabrication. A parametric study is conducted to evaluate the impact of four control factors—Young’s modulus of polyimide (PI), coefficient of thermal expansion (CTE) of PI, RDL thickness, and curing temperature—on warpage performance. The findings highlight that the warpage in the FO-LED is significantly affected by the CTE mismatch between the RDL, the LED, and the silicon substrate, with the properties of the PI material playing a crucial role. These insights offer valuable guidance for the design and optimization of robust FO-LED packages.