A PMOS-embedded low-voltage triggered silicon controlled rectifier ESD protection device for 3.3V I/O application

Abstract

In this paper, a novel low-trigger-voltage and high-robustness Electrostatic Discharge (ESD) protection device, called PMOS-embedded Low-Voltage Triggered Silicon Controlled Rectifier (PLVTSCR), is proposed for 3.3V I/O protection application in 0.18 μm CMOS process. The first improved PLVTSCR is called PLVTSCR-A. It is achieved by introducing a PMOS into the traditional SCR to provide a trigger current for SCR, thereby reducing the traditional SCR's trigger voltage (V_t1) and further increasing the failure current (I_t2) by utilizing the PMOS to introduce an additional parasitic SCR path. The second improved PLVTSCR is called PLVTSCR-B. The difference between PLVTSCR-B and PLVTSCR-A is that PLVTSCR-B does not have the DNW layer, making the base region of the parasitic NPN open circuit, further reducing PLVTSCR-A's trigger voltage. The third device is called PLVTSCR-C. PLVTSCR-C is another layout structure of PLVTSCR-B, and it can increase the holding current (I_h) and holding voltage of the device without increasing the area. The proposed series of devices can significantly improve the ESD characteristics of traditional SCR. Measurement results show that the PLVTSCR-C's trigger voltage is reduced by 51.5 %, and the failure current is increased by 10.3 % compared to traditional SCR. Furthermore, the holding current of PLVTSCR-C is 328.5 mA, which is much higher than the current during normal operation of the circuit and can effectively prevent latch-up. Additionally, the new device is expected to protect 3.3V I/O in deep submicron technology and has been implemented in a 0.18 μm CMOS process.