Design and verification of silicon bridge in 2.5D advanced package based on universal chiplet interconnect express (UCIe)

Abstract

This paper presents the design and verification of an embedded silicon bridge interconnect structure for 2.5D advanced packaging based on the Universal Chiplet Interconnect Express (UCIe). To enable high-speed, low-latency communication between chiplets, various routing patterns and transmission structures were explored. Layouts and test vehicles were designed with bump pitches of 45 μm and 55 μm and underwent fabrication for validation. Test results indicate that the silicon bridge demonstrates excellent signal integrity (SI) at a transmission rate of 32 Gbps, with S-parameter, Voltage Transfer Function (VTF) and eye diagram test results all meeting UCIe specifications for advanced packaging, highlighting the feasibility of this interconnect structure for high-density integration and high-speed transmission. This research provides a viable design and manufacturing solution for UCIe-based chiplet interconnects and validates the potential of embedded silicon bridges in heterogeneous integration applications.