Compact analytical modeling of underlap gate stack graded channel junction accumulation mode junctionless FET in subthreshold regime

Abstract

This paper presents the compact analytical model of underlap gate stack (GS) graded channel (GC) junction accumulation mode (JAM) junctionless (JL) FET. At first, a comparative analysis between the two different graded channel schemes and non-graded channel is performed based on I_ON, I_OFF and I_ON/I_OFF ratio. The scheme that yields the higher I_ON/I_OFF ratio along with smaller I_OFF, is adopted in the proposed JL FET for further analysis. The 2D analytical modeling of the GS-GC-JAM-JL FET deals with the determination of surface potential, threshold voltage, subthreshold drain current, DIBL and subthreshold swing. Results obtained from analytical model and simulations are compared and an excellent match is found. Thus the present paper establishes the outstanding ability of proposed underlap GS-GC-JAM-JL FET architecture to shield the short channel effects without sacrificing its performance, and therefore, proves it as a potential candidate for ultra-low power applications.