A Transient Resistance/Capacitance Network-Based Model for Heat Spreading in Substrate Stacks Having Multiple Anisotropic Layers

Abstract

Heat spreading from local, time-dependent heat sources in electronic packages results in the propagation of temperature non-uniformities through the stack of material layers attached to the chip. Available models either predict the chip temperatures only in the steady-state. We develop a transient resistance/capacitance network-based modeling approach capable of predicting the spatiotemporal temperature fields for this chip-on-stack geometry, accounting for in-plane heat spreading, through-plane heat conduction, and the effective convection resistance boundary conditions. The estimates from the present model are validated with direct comparison to a finite-volume numerical model for three-dimensional heat conduction. In the presence of a step heat input, the results demonstrate that the model accurately captures the transient temperature rise across the multi-substrate stack comprising layers with different anisotropic properties. For a case where the rectangular stack is exposed to a sinusoidally varying heat input the model is able to capture the general trends in the transient temperature fields in the plane where the heat source is applied to the multi-substrate stack. In summary, the developed resistance/capacitance network-based transient model offers a low-computational-cost method to predict the spatiotemporal temperature distribution over an arbitrary transient heat source interfacing a multi-layer stack of substrates.