Delamination failure is one of the most prevalent and serious reliability issues in microelectronic packaging. To understand this phenomenon further, this study constructs an experimental test system consisting of a double cantilever beam (DCB) fixture, an MTS-Acumen microforce tester, and a temperature and humidity controller. The system is employed to investigate the effects of coupled moisture-thermal loading on the critical strain energy release rate (SERR) at the EMC/Cu leadframe (LF) interface of a WQFN assembly. A three-dimensional (3D) computational model with hygro-thermal loading conditions is developed to evaluate the moisture diffusion, thermal stress, and integrated stress of a multi-chip WQFN package under typical processing conditions and precondition tests. The validated simulation model is then applied with the virtual crack closure technique (VCCT) to investigate the fracture behavior at the EMC/Cu LF interface in the WQFN package. The effects of three design parameters on the SERR performance of the package are identified through a parametric analysis. Finally, a Genetic Algorithm (GA) optimization method is employed to examine the effects of the main structural design parameters of the WQFN package on its delamination reliability. The results are used to determine the optimal packaging design that minimizes the SERR and hence enhances the package reliability.
{"title":"Effects of Thermal-Moisture Coupled Field On Delamination Behavior of Electronic Packaging","authors":"Meng-Kai Shih, Guan-Sian Lin, Jonny Yang","doi":"10.1115/1.4064355","DOIUrl":"https://doi.org/10.1115/1.4064355","url":null,"abstract":"\u0000 Delamination failure is one of the most prevalent and serious reliability issues in microelectronic packaging. To understand this phenomenon further, this study constructs an experimental test system consisting of a double cantilever beam (DCB) fixture, an MTS-Acumen microforce tester, and a temperature and humidity controller. The system is employed to investigate the effects of coupled moisture-thermal loading on the critical strain energy release rate (SERR) at the EMC/Cu leadframe (LF) interface of a WQFN assembly. A three-dimensional (3D) computational model with hygro-thermal loading conditions is developed to evaluate the moisture diffusion, thermal stress, and integrated stress of a multi-chip WQFN package under typical processing conditions and precondition tests. The validated simulation model is then applied with the virtual crack closure technique (VCCT) to investigate the fracture behavior at the EMC/Cu LF interface in the WQFN package. The effects of three design parameters on the SERR performance of the package are identified through a parametric analysis. Finally, a Genetic Algorithm (GA) optimization method is employed to examine the effects of the main structural design parameters of the WQFN package on its delamination reliability. The results are used to determine the optimal packaging design that minimizes the SERR and hence enhances the package reliability.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"19 11","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138951972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A relatively low-cost and easy-to-use strain gauge measurement is proposed here as an alternative method for simultaneously determining the thermally-induced warpages and the coefficients of thermal expansion (CTEs) of the flip-chip packages with a cap (or lid). The feasibility of the strain gauge method is evaluated by the shadow moiré experiment and the finite element analysis. The stiffness effect of the thermal interface materials (TIMs) in the flip-chip packages with a cap is also considered. The result suggests that the general back-to-back gauge measurement method on the top and bottom of the specimen would cause significant errors as the TIM is relatively compliant, but not for stiff TIMs. This study also proposes a modified gauge method with a few related strain equations for those cases with compliant TIMs to effectively determine their thermal warpages and CTEs by the gauge measurement. The finite element method (FEM) simulation, consistent with shadow moiré, has further validated the effectiveness of the modified gauge method. Therefore, the newly developed and modified method of strain gauges is found to be feasible and workable for simultaneously determining both thermal warpages and CTEs of the flip-chip packages with a cap, especially with a compliant TIM.
本文提出了一种成本相对较低且易于使用的应变片测量方法，作为同时测定带盖倒装芯片封装的热致翘曲和热膨胀系数（CTE）的替代方法。通过阴影摩尔纹实验和有限元分析评估了应变计方法的可行性。此外，还考虑了带盖倒装芯片封装中热界面材料（TIM）的刚度效应。结果表明，在试样顶部和底部采用一般的背靠背量规测量方法会因 TIM 的相对顺从性而导致重大误差，但对于刚性 TIM 则不会。本研究还针对具有顺应性 TIM 的情况，提出了一种改进的量规测量方法，其中包含一些相关的应变方程，可通过量规测量有效确定其热翘曲和 CTE。与阴影摩尔相一致的有限元法（FEM）模拟进一步验证了修正量规法的有效性。因此，新开发和改进的应变片方法对于同时确定带盖倒装芯片封装（尤其是兼容 TIM）的热翘曲和 CTE 是可行的。
{"title":"Simultaneous Characterization of Both Ctes and Thermal Warpages of Flip-Chip Packages with a Cap Using Strain Gauges","authors":"Yu Wen Wang, M. Tsai, Y. S. Chou","doi":"10.1115/1.4064354","DOIUrl":"https://doi.org/10.1115/1.4064354","url":null,"abstract":"\u0000 A relatively low-cost and easy-to-use strain gauge measurement is proposed here as an alternative method for simultaneously determining the thermally-induced warpages and the coefficients of thermal expansion (CTEs) of the flip-chip packages with a cap (or lid). The feasibility of the strain gauge method is evaluated by the shadow moiré experiment and the finite element analysis. The stiffness effect of the thermal interface materials (TIMs) in the flip-chip packages with a cap is also considered. The result suggests that the general back-to-back gauge measurement method on the top and bottom of the specimen would cause significant errors as the TIM is relatively compliant, but not for stiff TIMs. This study also proposes a modified gauge method with a few related strain equations for those cases with compliant TIMs to effectively determine their thermal warpages and CTEs by the gauge measurement. The finite element method (FEM) simulation, consistent with shadow moiré, has further validated the effectiveness of the modified gauge method. Therefore, the newly developed and modified method of strain gauges is found to be feasible and workable for simultaneously determining both thermal warpages and CTEs of the flip-chip packages with a cap, especially with a compliant TIM.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"68 5","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138948148","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yuan Chen, Zhongyang Wang, Yuhui Fan, Ming Dong, Dengxue Liu
In a highly competitive and demanding microelectronics market, non-destructive testing (NDT) technology has been widely applied to defect detection and evaluation of microelectronic packaging. However, the trend of microelectronic packaging toward miniaturization, high-density, ultra-thin, ultra-light and with small chip footprint, poses an urgent demand for novel NDT methods with high-resolution and large penetration depth, which is utilized for internal defect detection and identification of advanced complicated packages. The conventional NDT methods for microelectronic packaging mainly include optical visual inspection, X-ray inspection, active infrared thermography, scanning acoustic microscopy (SAM), atomic force microscopy (AFM), laser Doppler vibration measuring technique, scanning SQUID microscopy (SSM), electrical impedance spectroscopy (EIS), scanning electron microscope (SEM), and so on. This paper aims to provide a review of addressing their basic principles, advantages, limitations and application researches in the field of defect inspection of microelectronic packaging. Moreover, in order to overcome the shortcomings of the existing NDT methods, this paper emphasizes a novel NDT approach, called hybrid ultrasonic-laser digital holographic microscopy (DHM) imaging inspection method, and discusses its basic principle, merits, key techniques, system construction and experimental results in detail. When some key technical problems can be solved in further research, this method will become a potentially promising technique for defect detection and evaluation of advanced complicated packages.
{"title":"Research Status and Progress On Non-Destructive Testing Methods for Defect Inspection of Microelectronic Packaging","authors":"Yuan Chen, Zhongyang Wang, Yuhui Fan, Ming Dong, Dengxue Liu","doi":"10.1115/1.4064361","DOIUrl":"https://doi.org/10.1115/1.4064361","url":null,"abstract":"\u0000 In a highly competitive and demanding microelectronics market, non-destructive testing (NDT) technology has been widely applied to defect detection and evaluation of microelectronic packaging. However, the trend of microelectronic packaging toward miniaturization, high-density, ultra-thin, ultra-light and with small chip footprint, poses an urgent demand for novel NDT methods with high-resolution and large penetration depth, which is utilized for internal defect detection and identification of advanced complicated packages. The conventional NDT methods for microelectronic packaging mainly include optical visual inspection, X-ray inspection, active infrared thermography, scanning acoustic microscopy (SAM), atomic force microscopy (AFM), laser Doppler vibration measuring technique, scanning SQUID microscopy (SSM), electrical impedance spectroscopy (EIS), scanning electron microscope (SEM), and so on. This paper aims to provide a review of addressing their basic principles, advantages, limitations and application researches in the field of defect inspection of microelectronic packaging. Moreover, in order to overcome the shortcomings of the existing NDT methods, this paper emphasizes a novel NDT approach, called hybrid ultrasonic-laser digital holographic microscopy (DHM) imaging inspection method, and discusses its basic principle, merits, key techniques, system construction and experimental results in detail. When some key technical problems can be solved in further research, this method will become a potentially promising technique for defect detection and evaluation of advanced complicated packages.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"27 11","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-12-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"138951786","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, a variable density topology optimization method is used to design a high thermal conductivity path structure for efficient heat dissipation. The temperature and stiffness in the module volume are taken as the objective function. Simulations are carried out to compare with a high-power electronics device heat dissipation. The heat dissipation performance (HDP) of structures optimized topologically is further enhanced through the use of auxiliary materials, including highly thermally conductive coating material and phase change material (PCM). The efficient heat dissipation of the constructed topology optimization model and the effectiveness of the proposed method are verified.
{"title":"Heat Dissipation Design Based On Topology Optimization And Auxiliary Materials","authors":"Jiawei Chen, Zhongming Yan, Yang Qiao, Feihong Lin, Yu Wang, Hongcheng Zhou","doi":"10.1115/1.4064099","DOIUrl":"https://doi.org/10.1115/1.4064099","url":null,"abstract":"In this paper, a variable density topology optimization method is used to design a high thermal conductivity path structure for efficient heat dissipation. The temperature and stiffness in the module volume are taken as the objective function. Simulations are carried out to compare with a high-power electronics device heat dissipation. The heat dissipation performance (HDP) of structures optimized topologically is further enhanced through the use of auxiliary materials, including highly thermally conductive coating material and phase change material (PCM). The efficient heat dissipation of the constructed topology optimization model and the effectiveness of the proposed method are verified.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"130 6","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139256460","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A finite element simulation analysis model was developed for a PBGA assembly to analyze its behavior under thermal cyclic loading conditions. The stress distribution in the SAC305 solder joints at different locations within the array was investigated by using ANAND constitutive equations. Subsequently, the thermal fatigue life of the key solder joints was quantified. The study also examined the influence of the solder joint diameter, substrate thickness, solder joint height, PCB thickness, and mold compound height on solder joint stress. Optimization of assembly parameters was achieved through the application of the Taguchi method. An extensive analysis was conducted using different assembly parameter combinations, employing the L9(34) orthogonal array design to explore the thermal cycling effects. The computed average Von Mises stress Δσ for the critical thin-layer elements of solder joints located in hazardous positions within the assembly was notably affected by variations in the solder joint height, substrate thickness, solder joint diameter, and mold compound height. This impact ranked in descending order of significance as solder joint height, substrate thickness, solder joint diameter, and mold compound height. The optimal parameter combination determined was a solder joint height of 0.70 mm, a solder joint diameter of 0.85 mm, a substrate thickness of 0.51 mm, and a mold compound height of 1.12 mm. Implementing this optimized configuration led to a significant 4.07% reduction in average stress ?? for the critical thin-layer elements within hazardous solder joints. Moreover, the extension of the thermal fatigue life was notably improved, achieving an impressive 51.72% increase.
{"title":"Optimal Design of Thermal Cycling Reliability For PBGA Assembly via FEM and Taguchi Method","authors":"Chao Gao, Chunyue Huang, Ying Liang","doi":"10.1115/1.4064097","DOIUrl":"https://doi.org/10.1115/1.4064097","url":null,"abstract":"A finite element simulation analysis model was developed for a PBGA assembly to analyze its behavior under thermal cyclic loading conditions. The stress distribution in the SAC305 solder joints at different locations within the array was investigated by using ANAND constitutive equations. Subsequently, the thermal fatigue life of the key solder joints was quantified. The study also examined the influence of the solder joint diameter, substrate thickness, solder joint height, PCB thickness, and mold compound height on solder joint stress. Optimization of assembly parameters was achieved through the application of the Taguchi method. An extensive analysis was conducted using different assembly parameter combinations, employing the L9(34) orthogonal array design to explore the thermal cycling effects. The computed average Von Mises stress Δσ for the critical thin-layer elements of solder joints located in hazardous positions within the assembly was notably affected by variations in the solder joint height, substrate thickness, solder joint diameter, and mold compound height. This impact ranked in descending order of significance as solder joint height, substrate thickness, solder joint diameter, and mold compound height. The optimal parameter combination determined was a solder joint height of 0.70 mm, a solder joint diameter of 0.85 mm, a substrate thickness of 0.51 mm, and a mold compound height of 1.12 mm. Implementing this optimized configuration led to a significant 4.07% reduction in average stress ?? for the critical thin-layer elements within hazardous solder joints. Moreover, the extension of the thermal fatigue life was notably improved, achieving an impressive 51.72% increase.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"25 2","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139257986","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Jiantao Zhang, Zhengfang Chang, Haida Xu, Dong Qu, Xinyu Shi
Printed Circuit Board (PCB) is one of the most important components of electronic products. But the traditional defect detection methods are gradually difficult to meet the requirements of PCB defect detection. The research on PCB defect recognition method based on convolutional neural network is the current trend. The PCB defect image recognition based on DenseNet169 network model is studied in this paper. In order to reduce the omission of PCB defects in actual detection, it is necessary to further improve the sensitivity of the model. Therefore, a classification model based on the multi-model fusion of the DenseNet169 model and the ResNet50 model is proposed. At the same time, the network structure after multi-model fusion is improved. The improved multi-model fusion model Mix-Fusion enables the network to not only retain the recognition accuracy of the ResNet50 model for NG defects and small defect images, but also improve the overall recognition accuracy through the feature reuse and bypass settings of the DenseNet169 model. The experimental results show that when the threshold is 0.5, the sensitivity of the improved multi-model fusion network can reach 99.2%, and the specificity is 99.5%. The sensitivity of Mix-Fusion is 1.2% higher than that of DenseNet169. High sensitivity means fewer missed NG images, and high specificity means less workload for employees. The improved model improves sensitivity and maintains high specificity.
{"title":"PCB Defect Image Recognition Based On The Multi-Model Fusion Algorithm","authors":"Jiantao Zhang, Zhengfang Chang, Haida Xu, Dong Qu, Xinyu Shi","doi":"10.1115/1.4064098","DOIUrl":"https://doi.org/10.1115/1.4064098","url":null,"abstract":"Printed Circuit Board (PCB) is one of the most important components of electronic products. But the traditional defect detection methods are gradually difficult to meet the requirements of PCB defect detection. The research on PCB defect recognition method based on convolutional neural network is the current trend. The PCB defect image recognition based on DenseNet169 network model is studied in this paper. In order to reduce the omission of PCB defects in actual detection, it is necessary to further improve the sensitivity of the model. Therefore, a classification model based on the multi-model fusion of the DenseNet169 model and the ResNet50 model is proposed. At the same time, the network structure after multi-model fusion is improved. The improved multi-model fusion model Mix-Fusion enables the network to not only retain the recognition accuracy of the ResNet50 model for NG defects and small defect images, but also improve the overall recognition accuracy through the feature reuse and bypass settings of the DenseNet169 model. The experimental results show that when the threshold is 0.5, the sensitivity of the improved multi-model fusion network can reach 99.2%, and the specificity is 99.5%. The sensitivity of Mix-Fusion is 1.2% higher than that of DenseNet169. High sensitivity means fewer missed NG images, and high specificity means less workload for employees. The improved model improves sensitivity and maintains high specificity.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"16 4","pages":""},"PeriodicalIF":1.6,"publicationDate":"2023-11-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139259368","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
R. Khalid, E. Youssef, R. L. Amalfi, A. Ortega, A. P. Wemhoff
Abstract A thermosyphon-based modular cooling approach offers an energy efficient cooling solution with an increased potential for waste heat recovery. Central to the cooling system is an air-refrigerant finned tube heat exchanger (HX), where air is cooled by evaporating refrigerant. This work builds on a previously published two-dimensional (2D) model for the finned-tube HX by updating and validating the model using in-house experimental data collected from the proposed system using R1233zd(E) as the working fluid. The results show that key system variables such as refrigerant outlet quality, air and refrigerant outlet temperatures, and exchanger duty agree within 20% of their experimental counterparts. The validated model is then used to predict the mean heat transfer coefficient on the refrigerant side for each tube in the direction of airflow, indicating a maximum heat transfer coefficient of nearly 1200 W/(m2 K) for a HX duty of 5.3 kW among the tested cases. The validated model therefore enables accurate predictions of HX performance and provides insights into improving the heat exchange efficiency and the corresponding system performance.
{"title":"Validation and Application of a Finned Tube Heat Exchanger Model for Rack-Level Cooling","authors":"R. Khalid, E. Youssef, R. L. Amalfi, A. Ortega, A. P. Wemhoff","doi":"10.1115/1.4063252","DOIUrl":"https://doi.org/10.1115/1.4063252","url":null,"abstract":"Abstract A thermosyphon-based modular cooling approach offers an energy efficient cooling solution with an increased potential for waste heat recovery. Central to the cooling system is an air-refrigerant finned tube heat exchanger (HX), where air is cooled by evaporating refrigerant. This work builds on a previously published two-dimensional (2D) model for the finned-tube HX by updating and validating the model using in-house experimental data collected from the proposed system using R1233zd(E) as the working fluid. The results show that key system variables such as refrigerant outlet quality, air and refrigerant outlet temperatures, and exchanger duty agree within 20% of their experimental counterparts. The validated model is then used to predict the mean heat transfer coefficient on the refrigerant side for each tube in the direction of airflow, indicating a maximum heat transfer coefficient of nearly 1200 W/(m2 K) for a HX duty of 5.3 kW among the tested cases. The validated model therefore enables accurate predictions of HX performance and provides insights into improving the heat exchange efficiency and the corresponding system performance.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"112 13","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-10","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135137470","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Beihan Zhao, Aniket Bharamgonda, Edwin Quinn, George Stackhouse, Jason Fleischer, Michael Osterman, Michael Azarian, Daniel Hines, Siddhartha Das, Abhijit Dasgupta
Abstract Aerosol-Jet Printing (AJP) technology, applied to the manufacturing of printed hybrid electronics (PHE) devices, has the capability to fabricate highly complex structures with resolution in the tens-of-microns scale, creating new possibilities for the fabrication of electronic devices and assemblies. The widespread use of AJP in fabricating PHE and package-level electronics necessitates a thorough assessment of not only the performance of AJP printed electronics but also their reliability under different kinds of life-cycle operational and environmental stresses. One important hindrance to the reliability and long-term performance of such AJP electronics is electrochemical migration (ECM). ECM is an important failure mechanism in electronics under temperature and humidity conditions because it can lead to conductive dendritic growth, which can cause dielectric breakdown, leakage current, and unexpected short circuits. In this paper, the ECM propensity in conductive traces printed with AJP process, using silver-nanoparticle (AgNP) based inks, was experimentally studied using temperature-humidity-bias (THB) testing of printed test coupons. Conductive dendritic growth with complex morphologies was observed under different levels of temperature, humidity, and electric bias in the THB experiments. Weibull statistics are used to quantify the failure data, along with the corresponding confidence bounds to capture the uncertainty of the Weibull distribution. A nonmonotonic relationship between time-to-failure and electric field strength was noticed. An empirical acceleration model for ECM is proposed, by combining the classical Peck's model with a quadratic polynomial dependence on electric field strength. This model provides good estimate of acceleration factors for use conditions where the temperature, humidity, and electrical field are within the tested range, but should be extrapolated with care beyond the tested range.
{"title":"Temperature-Humidity-Bias Testing and Life Prediction Modeling for Electrochemical Migration in Aerosol-Jet Printed Circuits","authors":"Beihan Zhao, Aniket Bharamgonda, Edwin Quinn, George Stackhouse, Jason Fleischer, Michael Osterman, Michael Azarian, Daniel Hines, Siddhartha Das, Abhijit Dasgupta","doi":"10.1115/1.4063541","DOIUrl":"https://doi.org/10.1115/1.4063541","url":null,"abstract":"Abstract Aerosol-Jet Printing (AJP) technology, applied to the manufacturing of printed hybrid electronics (PHE) devices, has the capability to fabricate highly complex structures with resolution in the tens-of-microns scale, creating new possibilities for the fabrication of electronic devices and assemblies. The widespread use of AJP in fabricating PHE and package-level electronics necessitates a thorough assessment of not only the performance of AJP printed electronics but also their reliability under different kinds of life-cycle operational and environmental stresses. One important hindrance to the reliability and long-term performance of such AJP electronics is electrochemical migration (ECM). ECM is an important failure mechanism in electronics under temperature and humidity conditions because it can lead to conductive dendritic growth, which can cause dielectric breakdown, leakage current, and unexpected short circuits. In this paper, the ECM propensity in conductive traces printed with AJP process, using silver-nanoparticle (AgNP) based inks, was experimentally studied using temperature-humidity-bias (THB) testing of printed test coupons. Conductive dendritic growth with complex morphologies was observed under different levels of temperature, humidity, and electric bias in the THB experiments. Weibull statistics are used to quantify the failure data, along with the corresponding confidence bounds to capture the uncertainty of the Weibull distribution. A nonmonotonic relationship between time-to-failure and electric field strength was noticed. An empirical acceleration model for ECM is proposed, by combining the classical Peck's model with a quadratic polynomial dependence on electric field strength. This model provides good estimate of acceleration factors for use conditions where the temperature, humidity, and electrical field are within the tested range, but should be extrapolated with care beyond the tested range.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"79 ","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-11-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135011617","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Abstract Solder balls used in electronic packaging should have high dimensional and shape accuracy requirements to ensure the connection quality of solder balls during soldering. However, the existing solder ball detection methods were hard to measure the diameter and roundness in an integrated and fast manner. Therefore, a new method and device for measuring the diameter and roundness of solder balls was proposed based on machine vision technology, including detection device and software design. The experimental device could detect the parameters of at least 40 solder balls at a time. The solder ball image was preprocessed in the software system to improve the quality of the solder ball image, and then the Harris operator successfully detected the concave point on the bonded solder ball image and realized the solder ball separation based on the shortest path matching criterion. Compared with the SEM measurement value, the diameter and roundness of solder balls measured by the detection system were smaller than 3%.
{"title":"The Research For Quickly Measuring The Diameter And Roundness Of Solder Balls Based On Machine Vision Technology","authors":"Tongju Wang, Yahao Liu, Wenqian Zhang, Yongping Lei, Jian Lin, Hanguang Fu, Zipeng Lin","doi":"10.1115/1.4063918","DOIUrl":"https://doi.org/10.1115/1.4063918","url":null,"abstract":"Abstract Solder balls used in electronic packaging should have high dimensional and shape accuracy requirements to ensure the connection quality of solder balls during soldering. However, the existing solder ball detection methods were hard to measure the diameter and roundness in an integrated and fast manner. Therefore, a new method and device for measuring the diameter and roundness of solder balls was proposed based on machine vision technology, including detection device and software design. The experimental device could detect the parameters of at least 40 solder balls at a time. The solder ball image was preprocessed in the software system to improve the quality of the solder ball image, and then the Harris operator successfully detected the concave point on the bonded solder ball image and realized the solder ball separation based on the shortest path matching criterion. Compared with the SEM measurement value, the diameter and roundness of solder balls measured by the detection system were smaller than 3%.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"40 4","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136103640","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Chongyang Cai, Huayan Wang, Junbo Yang, Pengcheng Yin, Seungbae Park
Abstract Better understanding and control of residual stress in the chip build-up layer is becoming more and more important for the assembly process. To estimate the chip warpage and characterize the residual stress, different methods are proposed. However, most of them have high cost or some limitations for the upper build-up material. In this study, an innovative method is proposed to characterize the residual stress and predict the chip warpage behavior of different size chips at different temperatures. The method combines experimental inspection of chip warpage and finite element analysis. By reducing the silicon die thickness, the influence of residual stress in the build-up layer can be amplified. The residual stress can be obtained by inspecting the increased warpage when the silicon dies are reduced to different thicknesses. Correlating the thermal increase warpages of thinner chips can help characterize the effective modulus and CTE of the build-up layer. This study can help better understand the commonly classified build-up layer information. The results show good agreements between two types of samples under the same upstream process flow.
{"title":"A Comprehensive Study On Characterization Of Residual Stress Of Build-Up Layer And Prediction Of Chip Warpage","authors":"Chongyang Cai, Huayan Wang, Junbo Yang, Pengcheng Yin, Seungbae Park","doi":"10.1115/1.4063919","DOIUrl":"https://doi.org/10.1115/1.4063919","url":null,"abstract":"Abstract Better understanding and control of residual stress in the chip build-up layer is becoming more and more important for the assembly process. To estimate the chip warpage and characterize the residual stress, different methods are proposed. However, most of them have high cost or some limitations for the upper build-up material. In this study, an innovative method is proposed to characterize the residual stress and predict the chip warpage behavior of different size chips at different temperatures. The method combines experimental inspection of chip warpage and finite element analysis. By reducing the silicon die thickness, the influence of residual stress in the build-up layer can be amplified. The residual stress can be obtained by inspecting the increased warpage when the silicon dies are reduced to different thicknesses. Correlating the thermal increase warpages of thinner chips can help characterize the effective modulus and CTE of the build-up layer. This study can help better understand the commonly classified build-up layer information. The results show good agreements between two types of samples under the same upstream process flow.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":"91 3","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-10-30","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"136068605","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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