Bit Plane Slicing Chip Using Parallel Processing in Image Processing

Abstract

The objective of bit plane slicing (BPS) is to split the original image into different bit planes. The pixel values are first transformed into binary form and then split into bit planes. The research letter focuses on the concept of realizing the hardware chip for the BPS concept in which (8 × 8) image is configured into 8 planes. The realization is followed using the parallel processing in Xilinx ISE14.7 and functional verification of the planes is done in Modelsim 10.0.