Implementation of Ultrahigh-Speed Decimators

Abstract

Traditionally, the data rate of a digital signal processing system is bound by the processing speed. In this article, a formal approach for overcoming this limitation and allowing high-data-rate applications to run on relatively slow processors is presented. This approach allows the time sampling period to be much shorter than the time required to process an input sample; in effect, an ultrahigh-speed system is obtained where the sample rate exceeds the processing rate by a factor controlled by the system designer. The proposed approach is applied to the multirate decimation algorithm and its associated dependence graph. A directed acyclic graph (DAG) is then obtained from it using a scheduling policy. The DAG is then partitioned using an interlaced partitioning scheme. Multiphase/multirate clocking is used to synchronize the different components of the system. The number of partitions required depends on the I/O rate and processor speed. The proposed approach speeds up the system at the expense of extra latency and hardware resources.