Pub Date : 2020-10-26DOI: 10.1109/CJECE.2020.3005092
H. Fletcher, Andrew Macdonald, C. Secord, M. Lenckowski, Rajkumar Padmawar, Dennis K. Hore
This account details the design and construction of a sophisticated tracking wheel for the accelerated aging of polymer insulators by subjecting them to surface contamination and high voltage. Automated control of wet-dry cycles is achieved by means of a computer-controlled lift mechanism that operates in tandem with the rotation. The applied voltage is continuously variable and can accommodate insulators of mixed lengths. The design incorporates a fail-safe control system that automates the selected test cycle, provides an intuitive user interface, and integrates multiple safety measures. This is achieved by implementing a programmable logic controller with digital and analog inputs and outputs. An associated ladder logic program automates the actuation of electromechanical hardware while also processing the inputs provided from control hardware, such as limit switches, optical encoders, variable frequency drives, and sensors. A touch-screen human interface module provides feedback and allows the user a means of input. Programmed fault detection, flood sensors, and a trapped key system increase the level of user safety and provide environmental and infrastructure protection.
{"title":"Design and Construction of an Advanced Tracking Wheel for Insulator Materials Testing","authors":"H. Fletcher, Andrew Macdonald, C. Secord, M. Lenckowski, Rajkumar Padmawar, Dennis K. Hore","doi":"10.1109/CJECE.2020.3005092","DOIUrl":"https://doi.org/10.1109/CJECE.2020.3005092","url":null,"abstract":"This account details the design and construction of a sophisticated tracking wheel for the accelerated aging of polymer insulators by subjecting them to surface contamination and high voltage. Automated control of wet-dry cycles is achieved by means of a computer-controlled lift mechanism that operates in tandem with the rotation. The applied voltage is continuously variable and can accommodate insulators of mixed lengths. The design incorporates a fail-safe control system that automates the selected test cycle, provides an intuitive user interface, and integrates multiple safety measures. This is achieved by implementing a programmable logic controller with digital and analog inputs and outputs. An associated ladder logic program automates the actuation of electromechanical hardware while also processing the inputs provided from control hardware, such as limit switches, optical encoders, variable frequency drives, and sensors. A touch-screen human interface module provides feedback and allows the user a means of input. Programmed fault detection, flood sensors, and a trapped key system increase the level of user safety and provide environmental and infrastructure protection.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-10-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2020.3005092","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47751131","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-17DOI: 10.1109/CJECE.2020.2992010
Mohammed Shoukry, F. Gebali, P. Agathoklis
Traditionally, the data rate of a digital signal processing system is bound by the processing speed. In this article, a formal approach for overcoming this limitation and allowing high-data-rate applications to run on relatively slow processors is presented. This approach allows the time sampling period to be much shorter than the time required to process an input sample; in effect, an ultrahigh-speed system is obtained where the sample rate exceeds the processing rate by a factor controlled by the system designer. The proposed approach is applied to the multirate decimation algorithm and its associated dependence graph. A directed acyclic graph (DAG) is then obtained from it using a scheduling policy. The DAG is then partitioned using an interlaced partitioning scheme. Multiphase/multirate clocking is used to synchronize the different components of the system. The number of partitions required depends on the I/O rate and processor speed. The proposed approach speeds up the system at the expense of extra latency and hardware resources.
{"title":"Implementation of Ultrahigh-Speed Decimators","authors":"Mohammed Shoukry, F. Gebali, P. Agathoklis","doi":"10.1109/CJECE.2020.2992010","DOIUrl":"https://doi.org/10.1109/CJECE.2020.2992010","url":null,"abstract":"Traditionally, the data rate of a digital signal processing system is bound by the processing speed. In this article, a formal approach for overcoming this limitation and allowing high-data-rate applications to run on relatively slow processors is presented. This approach allows the time sampling period to be much shorter than the time required to process an input sample; in effect, an ultrahigh-speed system is obtained where the sample rate exceeds the processing rate by a factor controlled by the system designer. The proposed approach is applied to the multirate decimation algorithm and its associated dependence graph. A directed acyclic graph (DAG) is then obtained from it using a scheduling policy. The DAG is then partitioned using an interlaced partitioning scheme. Multiphase/multirate clocking is used to synchronize the different components of the system. The number of partitions required depends on the I/O rate and processor speed. The proposed approach speeds up the system at the expense of extra latency and hardware resources.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-09-17","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2020.2992010","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43224595","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-09DOI: 10.1109/CJECE.2020.2978265
Jiayi Fan, Yongkeun Lee
This article introduces a concept to extend the base speed of a switched reluctance motor (SRM) from the perspective of the motor’s design. Conventionally, designs prioritize a high saliency of SRM in order to produce more torque with the same current. However, the speed range is limited in the conventional design. The back EMF is the key factor that restricts the speed of the SRM from further increasing due to its strong reaction to the phase terminal voltage applied, which is especially severe at high-speed operation. Therefore, in this article, the design of an SRM with a lower inductance slope is proposed. The reduction of the motor’s saliency in the proposed idea can effectively diminish the back EMF; thus an extended base speed and wider constant torque range can be achieved. Comparative simulation results from the conventionally designed motor and the motor designed by the proposed idea are given, which demonstrate that the base speed is enhanced and the current control can be maintained at a higher speed in the proposed idea.
{"title":"Design Consideration to Achieve Wide-Speed-Range Operation in a Switched Reluctance Motor","authors":"Jiayi Fan, Yongkeun Lee","doi":"10.1109/CJECE.2020.2978265","DOIUrl":"https://doi.org/10.1109/CJECE.2020.2978265","url":null,"abstract":"This article introduces a concept to extend the base speed of a switched reluctance motor (SRM) from the perspective of the motor’s design. Conventionally, designs prioritize a high saliency of SRM in order to produce more torque with the same current. However, the speed range is limited in the conventional design. The back EMF is the key factor that restricts the speed of the SRM from further increasing due to its strong reaction to the phase terminal voltage applied, which is especially severe at high-speed operation. Therefore, in this article, the design of an SRM with a lower inductance slope is proposed. The reduction of the motor’s saliency in the proposed idea can effectively diminish the back EMF; thus an extended base speed and wider constant torque range can be achieved. Comparative simulation results from the conventionally designed motor and the motor designed by the proposed idea are given, which demonstrate that the base speed is enhanced and the current control can be maintained at a higher speed in the proposed idea.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2020.2978265","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48739725","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-09DOI: 10.1109/CJECE.2020.2991404
Samer J. Alabed
Many noncoherent distributed strategies for cooperative sensor networks that do not require channel knowledge at any antenna to overcome the overhead involved in channel estimation are lately suggested; however, these strategies suffer from low system performance in terms of bit error rate (BER) and a comparably high decoding complexity. Differential beamforming strategies have recently been proposed to overcome these problems; however, they are implemented using the four-phase protocol. Thus, we propose a new strategy based on the three-phase protocol to increase the symbol rate. By doing this, a significant improvement can be achieved in the overall system performance. Hence, in this article, a new bidirectional differential beamforming strategy is suggested: 1) to be applied on the three-phase protocol instead of the four-phase protocol; 2) to be applicable for a decentralized wireless sensor network using single-antenna sensors distributed randomly between the communicating base stations; 3) to enjoy low decoding complexity; and 4) to improve the network performance in terms of BER by maximizing the received signal-to-noise ratio at the receiving base station without requiring channel knowledge at any antenna in the whole network. From our simulation results, the proposed strategy shows a substantially improved BER performance compared with the current state-of-the-art ones.
{"title":"Noncoherent Distributed Beamforming in Decentralized Two-Way Relay Networks","authors":"Samer J. Alabed","doi":"10.1109/CJECE.2020.2991404","DOIUrl":"https://doi.org/10.1109/CJECE.2020.2991404","url":null,"abstract":"Many noncoherent distributed strategies for cooperative sensor networks that do not require channel knowledge at any antenna to overcome the overhead involved in channel estimation are lately suggested; however, these strategies suffer from low system performance in terms of bit error rate (BER) and a comparably high decoding complexity. Differential beamforming strategies have recently been proposed to overcome these problems; however, they are implemented using the four-phase protocol. Thus, we propose a new strategy based on the three-phase protocol to increase the symbol rate. By doing this, a significant improvement can be achieved in the overall system performance. Hence, in this article, a new bidirectional differential beamforming strategy is suggested: 1) to be applied on the three-phase protocol instead of the four-phase protocol; 2) to be applicable for a decentralized wireless sensor network using single-antenna sensors distributed randomly between the communicating base stations; 3) to enjoy low decoding complexity; and 4) to improve the network performance in terms of BER by maximizing the received signal-to-noise ratio at the receiving base station without requiring channel knowledge at any antenna in the whole network. From our simulation results, the proposed strategy shows a substantially improved BER performance compared with the current state-of-the-art ones.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2020.2991404","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43532459","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-09-09DOI: 10.1109/CJECE.2020.2984602
L. Taha, E. Abdel-Raheem
This article presents two new approaches of fetal electrocardiogram (ECG) signal (FECG) separation using the input-mode adaptive filter (IMAF) and the output-mode adaptive filter (OMAF). Both approaches use the recursive least-squares (RLS) and the least-mean-squares (LMS) algorithms and a single-reference-generation block. In the IMAF, the filter’s primary input is connected directly to the abdominal signal. The reference signal is generated by windowing the abdominal signal according to the locations of the QRS MECG pulses. In the OMAF, the filter’s primary input is connected to the output stage of a blind source separation block. The reference signal is generated by windowing the raw FECG signal, from the BSS output, according to the locations of the QRS pulses of the extracted MECG signal. We selected the null space idempotent transformation matrix (NSITM) as the BSS algorithm used in this work. Results from real Daisy and Physionet databases show the successful extraction of the FECG signal. Results from synthesized data from Physionet databases, using OMAF, show considerable improvement in extraction performances over NSITM and IMAF when the fetal-to-maternal signal-to-noise ratio (fmSNR) increases from −30 to 0 dB. This study demonstrated that the OMAF is a feasible algorithm for FECG extraction.
{"title":"Fetal ECG Extraction Using Input-Mode and Output-Mode Adaptive Filters With Blind Source Separation","authors":"L. Taha, E. Abdel-Raheem","doi":"10.1109/CJECE.2020.2984602","DOIUrl":"https://doi.org/10.1109/CJECE.2020.2984602","url":null,"abstract":"This article presents two new approaches of fetal electrocardiogram (ECG) signal (FECG) separation using the input-mode adaptive filter (IMAF) and the output-mode adaptive filter (OMAF). Both approaches use the recursive least-squares (RLS) and the least-mean-squares (LMS) algorithms and a single-reference-generation block. In the IMAF, the filter’s primary input is connected directly to the abdominal signal. The reference signal is generated by windowing the abdominal signal according to the locations of the QRS MECG pulses. In the OMAF, the filter’s primary input is connected to the output stage of a blind source separation block. The reference signal is generated by windowing the raw FECG signal, from the BSS output, according to the locations of the QRS pulses of the extracted MECG signal. We selected the null space idempotent transformation matrix (NSITM) as the BSS algorithm used in this work. Results from real Daisy and Physionet databases show the successful extraction of the FECG signal. Results from synthesized data from Physionet databases, using OMAF, show considerable improvement in extraction performances over NSITM and IMAF when the fetal-to-maternal signal-to-noise ratio (fmSNR) increases from −30 to 0 dB. This study demonstrated that the OMAF is a feasible algorithm for FECG extraction.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-09-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2020.2984602","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43884724","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-21DOI: 10.1109/CJECE.2019.2897277
Reza Avazeh, N. Yazdani
Ternary content addressable memories (TCAMs) have a lookup complexity of O(1). They require just one memory access to find an entry. For this reason, they are widely used in core routers of the Internet to achieve high packet forwarding capacities in terms of several 100 Gb/s. However, in a TCAM, the routing table needs to be stored in a sorted order according to the prefix length of the entries. Therefore, if a new entry needs to be added or an old one needs to be deleted, some other entries should be moved around to open a place for the new entry or fill the place of the old one. Practical methods to update a routing table require locking the TCAM during the update process. Therefore, this will cause a large number of packets to be dropped. This is because in the core routers of the Internet, the packets arrive at very high rates, and the routing table updates are very frequent. In this paper, we introduce a new, yet simple TCAM architecture in which entries do not need to be sorted. This means that updating the routing table will be done with a complexity of O(1), and therefore, no packets will be dropped.
{"title":"A New TCAM Architecture for IP Routing With Update Complexity Equal to O(1)","authors":"Reza Avazeh, N. Yazdani","doi":"10.1109/CJECE.2019.2897277","DOIUrl":"https://doi.org/10.1109/CJECE.2019.2897277","url":null,"abstract":"Ternary content addressable memories (TCAMs) have a lookup complexity of O(1). They require just one memory access to find an entry. For this reason, they are widely used in core routers of the Internet to achieve high packet forwarding capacities in terms of several 100 Gb/s. However, in a TCAM, the routing table needs to be stored in a sorted order according to the prefix length of the entries. Therefore, if a new entry needs to be added or an old one needs to be deleted, some other entries should be moved around to open a place for the new entry or fill the place of the old one. Practical methods to update a routing table require locking the TCAM during the update process. Therefore, this will cause a large number of packets to be dropped. This is because in the core routers of the Internet, the packets arrive at very high rates, and the routing table updates are very frequent. In this paper, we introduce a new, yet simple TCAM architecture in which entries do not need to be sorted. This means that updating the routing table will be done with a complexity of O(1), and therefore, no packets will be dropped.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2019.2897277","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47932949","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-21DOI: 10.1109/CJECE.2020.2971732
Jiayi Fan, Yongkeun Lee
This article develops a novel average torque control (ATC) scheme for switched reluctance (SR) motor on the basis of a brand-new microstep flux–current locus controller. The proposed ATC is based on the calculation of the average torque from the converted mechanical energy that can be illustrated as an enclosed area in a flux–current plane. It has the superior advantage that it is able to control the average torque over any arbitrary small-angle intervals, whereas the conventional ATC can control only the average torque for a whole stroke. In order to realize the proposed ATC, a flux–current locus controller, which consists of a hybrid flux controller and current controller as well as involve the microstep process, is introduced in this article. The flux–current locus of the energy conversion loop is controlled for the first time in the literature. With the locus controller, it is possible to achieve a better energy conversion ratio and the ATC. In order to verify both the proposed locus control method and the ATC for SR motor, detailed simulation results and discussion are provided.
{"title":"A Novel Average Torque Control of Switched Reluctance Motor Based on Flux–Current Locus Control","authors":"Jiayi Fan, Yongkeun Lee","doi":"10.1109/CJECE.2020.2971732","DOIUrl":"https://doi.org/10.1109/CJECE.2020.2971732","url":null,"abstract":"This article develops a novel average torque control (ATC) scheme for switched reluctance (SR) motor on the basis of a brand-new microstep flux–current locus controller. The proposed ATC is based on the calculation of the average torque from the converted mechanical energy that can be illustrated as an enclosed area in a flux–current plane. It has the superior advantage that it is able to control the average torque over any arbitrary small-angle intervals, whereas the conventional ATC can control only the average torque for a whole stroke. In order to realize the proposed ATC, a flux–current locus controller, which consists of a hybrid flux controller and current controller as well as involve the microstep process, is introduced in this article. The flux–current locus of the energy conversion loop is controlled for the first time in the literature. With the locus controller, it is possible to achieve a better energy conversion ratio and the ATC. In order to verify both the proposed locus control method and the ATC for SR motor, detailed simulation results and discussion are provided.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2020.2971732","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"43179746","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-08-21DOI: 10.1109/CJECE.2019.2962147
Ali Sadeghi, Mina Zolfy Lighvan, P. Prinetto
Using dynamic partial reconfiguration (DPR) feature in field-programmable gate array (FPGA) systems seems inevitable by considering the tremendous benefits, such as reduced cost and power. Nowadays, manual floorplanning is one of the difficulties in implementing DPR systems, which relies on the designer’s views and his command over designing the concepts for arranging the modules on the physical layout of the FPGA more efficiently, as the results of floorplanning can influence the next stages, such as the placement. In other words, placement and floorplanning that are separately conducted in the today’s tools are interdependent and the floorplanning results play a role in the placement and vice versa. This article aimed to propose a method for conducting floorplanning and placement simultaneously in DPR systems according to the genetic algorithm (GA). The proposed algorithm was tested on 20 largest MCNC benchmark circuits with DPR-support capability. Based on the results, wirelength and critical path delay improved by 14% and 17%, respectively, compared with Xilinx’s early access partial reconfiguration design flow (EAPR). However, area and runtime increased by about 2% and 8%, respectively. The proposed method was also compared with other research that uses B* tree and simulated annealing algorithm. The results showed that our proposed algorithm is competitive in various parameters with other research.
{"title":"Automatic and Simultaneous Floorplanning and Placement in Field-Programmable Gate Arrays With Dynamic Partial Reconfiguration Based on Genetic Algorithm","authors":"Ali Sadeghi, Mina Zolfy Lighvan, P. Prinetto","doi":"10.1109/CJECE.2019.2962147","DOIUrl":"https://doi.org/10.1109/CJECE.2019.2962147","url":null,"abstract":"Using dynamic partial reconfiguration (DPR) feature in field-programmable gate array (FPGA) systems seems inevitable by considering the tremendous benefits, such as reduced cost and power. Nowadays, manual floorplanning is one of the difficulties in implementing DPR systems, which relies on the designer’s views and his command over designing the concepts for arranging the modules on the physical layout of the FPGA more efficiently, as the results of floorplanning can influence the next stages, such as the placement. In other words, placement and floorplanning that are separately conducted in the today’s tools are interdependent and the floorplanning results play a role in the placement and vice versa. This article aimed to propose a method for conducting floorplanning and placement simultaneously in DPR systems according to the genetic algorithm (GA). The proposed algorithm was tested on 20 largest MCNC benchmark circuits with DPR-support capability. Based on the results, wirelength and critical path delay improved by 14% and 17%, respectively, compared with Xilinx’s early access partial reconfiguration design flow (EAPR). However, area and runtime increased by about 2% and 8%, respectively. The proposed method was also compared with other research that uses B* tree and simulated annealing algorithm. The results showed that our proposed algorithm is competitive in various parameters with other research.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-08-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2019.2962147","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"48615160","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-05-20DOI: 10.1109/CJECE.2019.2920938
Jinho Kim, S. Gadsden, S. Wilkerson
Over the past several decades, there has been a constant increase in the use of unmanned aircraft systems (UASs). Hence, there has also been a growth in the number of control algorithms to service many applications embodied by these vehicles. Initially, UASs were made popular by the military for reconnaissance, intelligence, surveillance, and target acquisition (RISTA) applications. Nowadays, UASs are used for everything from crop surveys to tourism. Nowhere is this more evident than with a multi-rotor unmanned aerial vehicle (UAV). This paper presents a survey of control methods for multi-rotor systems, namely quadrotors. In doing so, we hope to visualize a clear path to what additional capabilities might be needed in the future. In our examination, we review many of the notable research organizations and their efforts to expand the utility of multi-rotor aircraft. We also summarize the basic literature definitions and control strategies for autonomous quadrotors.
{"title":"A Comprehensive Survey of Control Strategies for Autonomous Quadrotors","authors":"Jinho Kim, S. Gadsden, S. Wilkerson","doi":"10.1109/CJECE.2019.2920938","DOIUrl":"https://doi.org/10.1109/CJECE.2019.2920938","url":null,"abstract":"Over the past several decades, there has been a constant increase in the use of unmanned aircraft systems (UASs). Hence, there has also been a growth in the number of control algorithms to service many applications embodied by these vehicles. Initially, UASs were made popular by the military for reconnaissance, intelligence, surveillance, and target acquisition (RISTA) applications. Nowadays, UASs are used for everything from crop surveys to tourism. Nowhere is this more evident than with a multi-rotor unmanned aerial vehicle (UAV). This paper presents a survey of control methods for multi-rotor systems, namely quadrotors. In doing so, we hope to visualize a clear path to what additional capabilities might be needed in the future. In our examination, we review many of the notable research organizations and their efforts to expand the utility of multi-rotor aircraft. We also summarize the basic literature definitions and control strategies for autonomous quadrotors.","PeriodicalId":55287,"journal":{"name":"Canadian Journal of Electrical and Computer Engineering-Revue Canadienne De Genie Electrique et Informatique","volume":null,"pages":null},"PeriodicalIF":1.7,"publicationDate":"2020-05-20","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/CJECE.2019.2920938","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47696288","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2020-02-07DOI: 10.1109/CJECE.2019.2953049
Farnaz Davardoost, Amin Babazadeh Sangar, K. Majidzadeh
Today, the relational database is not suitable for data management due to the large variety and volume of data which are mostly untrusted. Therefore, NoSQL has attracted the attention of companies. Despite it being a proper choice for managing a variety of large volume data, there is a big challenge and difficulty in performing online analytical processing (OLAP) on NoSQL since it is schema-less. This article aims to introduce a model to overcome null value in converting document-oriented NoSQL databases into relational databases using parallel similarity techniques. The proposed model includes four phases, shingling, chunck, minhashing, and locality-sensitive hashing MapReduce (LSHMR). Each phase performs a proper process on input NoSQL databases. The main idea of LSHMR is based on the nature of both locality-sensitive hashing (LSH) and MapReduce (MR). In this article, the LSH similarity search technique is used on the MR framework to extract OLAP cubes. LSH is used to decrease the number of comparisons. Furthermore, MR enables efficient distributed and parallel computing. The proposed model is an efficient and suitable approach for extracting OLAP cubes from an NoSQL database.
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