Low-Power Highly Reliable SET-Induced Dual-Node Upset-Hardened Latch and Flip-Flop

Abstract

It appears that the relentless pursuit of Moore’s law scaling from one generation of process technology to the next increases circuit vulnerability to single-event transient (SET)-induced double-node upset (SEDU). In this paper, we present a novel SEDU-hardened latch. The latch consists of a new 16-transistor (16T) SEDU-hardened storage cell and a C-type output buffer. The latch exhibits 25% lower power consumption, is 81% faster, and also shows 86% lower power-delay product than the existing SEDU-hardened latches. In addition, we present the first SEDU-hardened flip-flop that exhibits negative hold time. The proposed SEDU-hardened flip-flop is 29% faster, consumes 50% lower dynamic power and 25% lower static power, has 45% lower setup time, and uses 27% lower area than the existing partial SEDU-hardened flip-flop.