Chip Level Thermal Performance Measurements in Two-Phase Immersion Cooling

IF 2.2 4区 工程技术 Q3 ENGINEERING, ELECTRICAL & ELECTRONIC Journal of Electronic Packaging Pub Date : 2023-04-26 DOI:10.1115/1.4062403
Jimil M. Shah, Thomas E. Crandall, P. Tuma
{"title":"Chip Level Thermal Performance Measurements in Two-Phase Immersion Cooling","authors":"Jimil M. Shah, Thomas E. Crandall, P. Tuma","doi":"10.1115/1.4062403","DOIUrl":null,"url":null,"abstract":"\n Two-Phase Immersion cooling (2PIC) has been proposed as a means of economically increasing overall energy efficiency while accommodating increased chip powers and system-level power density. Designers unfamiliar with Two-phase immersion technology may be unaware of the chip-level thermal performance capabilities of the technology. This performance, in the case of a lidded processor, is quantified as a case-to-fluid thermal resistance, Rcf. This work made use of boiler assemblies comprised of copper plates to which two porous metallic boiling enhancement coatings (BECs) had been applied. These boiler assemblies were applied with conventional thermal grease to a thermal test vehicle (TTV) emulating the Skylake series of 8th Gen Intel® Xeon® CPUs and a thermal test slug (TTS) emulating the AMD EPYCTM processors. Both were tested in saturated 3MTM FluorinertTM FC-3284 fluid. The lowest Rcf=0.020 °C/W was achieved on the TTS at 350W. The paper also includes additional TTS data gathered with different boiler assemblies and Thermal Interface Materials as well as field data in the form of Rcf or junction-to-fluid thermal resistances, Rjf, for different live silicon chips.","PeriodicalId":15663,"journal":{"name":"Journal of Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":2.2000,"publicationDate":"2023-04-26","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Journal of Electronic Packaging","FirstCategoryId":"5","ListUrlMain":"https://doi.org/10.1115/1.4062403","RegionNum":4,"RegionCategory":"工程技术","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
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Abstract

Two-Phase Immersion cooling (2PIC) has been proposed as a means of economically increasing overall energy efficiency while accommodating increased chip powers and system-level power density. Designers unfamiliar with Two-phase immersion technology may be unaware of the chip-level thermal performance capabilities of the technology. This performance, in the case of a lidded processor, is quantified as a case-to-fluid thermal resistance, Rcf. This work made use of boiler assemblies comprised of copper plates to which two porous metallic boiling enhancement coatings (BECs) had been applied. These boiler assemblies were applied with conventional thermal grease to a thermal test vehicle (TTV) emulating the Skylake series of 8th Gen Intel® Xeon® CPUs and a thermal test slug (TTS) emulating the AMD EPYCTM processors. Both were tested in saturated 3MTM FluorinertTM FC-3284 fluid. The lowest Rcf=0.020 °C/W was achieved on the TTS at 350W. The paper also includes additional TTS data gathered with different boiler assemblies and Thermal Interface Materials as well as field data in the form of Rcf or junction-to-fluid thermal resistances, Rjf, for different live silicon chips.
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芯片级热性能测量在两相浸没冷却
两相浸入式冷却(2PIC)已被提出作为经济地提高整体能源效率的手段,同时适应增加的芯片功率和系统级功率密度。不熟悉两相浸没技术的设计人员可能不知道该技术的芯片级热性能。这种性能,在有盖处理器的情况下,被量化为外壳对流体的热阻,Rcf。这项工作使用了由铜板组成的锅炉组件,铜板上涂有两层多孔金属沸腾增强涂层(BECs)。这些锅炉组件与传统的导热油脂应用于模拟Skylake系列第八代Intel®Xeon®cpu的热测试车(TTV)和模拟AMD EPYCTM处理器的热测试段(TTS)。两者都在饱和3MTM FluorinertTM FC-3284流体中进行了测试。在350W时,TTS的Rcf最低为0.020°C/W。本文还包括了通过不同的锅炉组件和热界面材料收集的额外TTS数据,以及不同硅芯片的Rcf或结液热阻(Rjf)形式的现场数据。
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来源期刊
Journal of Electronic Packaging
Journal of Electronic Packaging 工程技术-工程:电子与电气
CiteScore
4.90
自引率
6.20%
发文量
44
审稿时长
3 months
期刊介绍: The Journal of Electronic Packaging publishes papers that use experimental and theoretical (analytical and computer-aided) methods, approaches, and techniques to address and solve various mechanical, materials, and reliability problems encountered in the analysis, design, manufacturing, testing, and operation of electronic and photonics components, devices, and systems. Scope: Microsystems packaging; Systems integration; Flexible electronics; Materials with nano structures and in general small scale systems.
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