Process-Recipe Development for Printing of Multi-Layer Circuitry with Z-Axis Interconnects Using Aerosol-Jet Printed Dielectric Vias

Abstract

Flexible electronics is emerging as a new consumer-industry phenomenon. Until now, the work primarily focuses on single-layer printing, taking into account different parameters such as mass flow, line width, sintering conditions, and overspray. The conventional PCBs are multi-layered, and multi-layer stacking of interconnections and establishing z-axis connections through vias similar to conventional PCBs are necessary for the flexible PCB to be used in the real world. Aerosol printing method gives us a broad aspect of establishing the interconnections depending on the various available inks such as silver, copper, carbon etc. Process recipes for manufacturing multilayer circuits and system scale-up methods are required. This paper aims to establish interconnections in the z-axis with the help of Aerosol printable silver ink and dielectric polyimide ink. Formulate process recipes needed to produce multilayer circuits and process scale-up methods. Sintering profile influences the conductivity and shear load value of the printed conductive metal layers requiring process optimization for multilayer builds. The printed conductive lines would undergo different sintering conditions and would then be tested for parameters such as interconnect resistance and shear load to failure. This paper explores the printing of multi-layer up to 8 conductive layers. Sintering profile for lower resistance per unit length and higher shear load to failure was tested.