Optimization of PCB SI Coupon Design That Minimizes Discontinuity Through via-in-Pad Plated over (VIPPO) Technique

Abstract

The importance of signal integrity is emphasized as signal speed increases, and higher frequencies are applied. The PCB manufacturer uses SI coupons that can replace the in-product circuit to measure and calculate the signal loss. In this study, we tried to minimize the discontinuous path of Delta-L coupon by using the VIPPO (Via In Pad Plated Over) technique to improve the signal integrity. We compared the VIPPO-applied design that has minimal discontinuity with the conventional Delta-L design. In order to minimize discontinuity, circuits connected to pads and via holes were removed from the outer layer, and the pads were designed directly above the via holes. First of all, we simulated the optimized design that eliminated discontinuities using Signal Integrity Software, Simbeor. Second, we measured and verified DeltaL by using Introbotix's Accu-prober program. In the future, higher measurement frequencies will further increase signal loss due to unnecessary pathways and discrete signals, therefore minimizing the effects of discontinuity will be an important issue, and using the VIPPO technique will help to improve signal integrity. Introduction In order to increase the speed of the signal, high frequency is applied, which emphasizes the importance of signal integrity. Many methods have been introduced to prevent noise and loss of signals such as low dielectric constant materials or low roughness surfaces. However, there are inherent components in the PCB structure that interfere with the signal quality, and how to remove them is also important. The Via-In-Pad Plated Over (VIPPO) structure has been adopted in many BGA footprint designs within the PCB. These VIPPO structures are preferred over the more traditional dogbone pad structure in order to shrink signal path lengths, reducing two parasitic effects, capacitance and inductance, for improved high-speed performance. The signal traces, which connect the BGA pads with the vias, act as inductors. Additionally, as high-speed designs typically have ground planes immediately below the outer layer, there is also a capacitive effect that is generated. With the VIPPO structure, the outer trace layer is eliminated, thereby cancelling both parasitic effects. In the PCB manufacturing process, a coupon for measuring signal loss is inserted outside and analyzed as one way to verify the characteristics of the signal. Coupons are methods for verifying on behalf of the actual products and it is important to make them as identical as possible to the product. Developed by Intel, the Delta-L coupon measures a long, short circuit and calculates the tow differences to extract the loss. The greatest feature of Delta-L is a simplified deembedding methodology to accurately measure stripline loss by using two test structures, long and short stripline traces, to remove unwanted effect, such as vias. The condition algorithm can eliminate the loss value variation induced by the multi-reflections between these impedance mismatches. Probe type is measurable and is applied to mass products due to its short measurement time. In this study, the effect of structure with minimized discontinuity path on signal loss using VIPPO process is analyzed using Delta-L coupon. Methods 1. Design of Delta-L Coupon with Minimized Discontinuity Representative methods of measuring signal loss include SMA connector type and probe type. The SMA connector is tightened at the end of the cable to minimize noise and improve accuracy, but the disadvantage is that it takes time to fasten and dismantle. On the other hand, the probe type is connected to the probe at the end of cable and connected to the PCB circuit from the probe, causing noise to the probe and difficulty in the calibration to the end of the probe, but the measurement time is short, so it is widely used for mass production by PCB manufacturers. Litek Company’s differential probe used in this study is a structure that contacts signal and ground at the same time as figure 1. The pins of probe are fixed so that the signal pad spacing of the outer layer is the same. As originally published in the SMTA Proceedings