Haijie Chen, Ziyao Bian, Tao Liu, Jielei Xie, Jingyu Wu, Yaojian Lin, Choon Heung Lee
The concept of chiplet was proposed in the post- Moore era. How to layout the multiple chips with different processes and sizes in the package structure is a problem that needs to be considered as different layouts may significantly affect the manufacturability during the packaging process. XDFOI-O is a 2.5D organic interposer structure with a significant coefficient of thermal expansion mismatch in it. Different layouts may cause excessive stress concentration in the package structure, as well as large wafer warpage, which can affect the normal operations of the production line. Stress accumulation on specific chiplet during the wafer thinning process is another manufacturability problem, leading to chip cracking. Prospective finite element analysis can be applied to evaluate the various layouts. In simulation work, different placement processes of dummy chips as stiffeners, as well as different chiplet thicknesses and underfill coverage, can be used as factors for simulation studies, thereby making a reference for further chiplet package design.
{"title":"Study on the Manufacturability of X Dimension Fan Out Integration Package with Organic RDLs (XDFOI-O)","authors":"Haijie Chen, Ziyao Bian, Tao Liu, Jielei Xie, Jingyu Wu, Yaojian Lin, Choon Heung Lee","doi":"10.4071/001c.115496","DOIUrl":"https://doi.org/10.4071/001c.115496","url":null,"abstract":"The concept of chiplet was proposed in the post- Moore era. How to layout the multiple chips with different processes and sizes in the package structure is a problem that needs to be considered as different layouts may significantly affect the manufacturability during the packaging process. XDFOI-O is a 2.5D organic interposer structure with a significant coefficient of thermal expansion mismatch in it. Different layouts may cause excessive stress concentration in the package structure, as well as large wafer warpage, which can affect the normal operations of the production line. Stress accumulation on specific chiplet during the wafer thinning process is another manufacturability problem, leading to chip cracking. Prospective finite element analysis can be applied to evaluate the various layouts. In simulation work, different placement processes of dummy chips as stiffeners, as well as different chiplet thicknesses and underfill coverage, can be used as factors for simulation studies, thereby making a reference for further chiplet package design.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"34 5","pages":""},"PeriodicalIF":0.0,"publicationDate":"2024-01-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"140526454","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
B. Klein, A. Allerman, A. Baca, C. Nordquist, A. Armstrong, M. V. Van Heukelom, A. Rice, V. Patel, M. Rosprim, L. Caravello, R. DeBerry, J. Pipkin, V. Abate, R. Kaplar
We report on AlGaN HEMT-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data revealed the GaN-channel HEMT experienced a 6.9× reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200 nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.
{"title":"AlGaN High Electron Mobility Transistor for High-Temperature Logic","authors":"B. Klein, A. Allerman, A. Baca, C. Nordquist, A. Armstrong, M. V. Van Heukelom, A. Rice, V. Patel, M. Rosprim, L. Caravello, R. DeBerry, J. Pipkin, V. Abate, R. Kaplar","doi":"10.4071/imaps.1832996","DOIUrl":"https://doi.org/10.4071/imaps.1832996","url":null,"abstract":"We report on AlGaN HEMT-based logic development, using combined enhancement- and depletion-mode transistors to fabricate inverters with operation from room temperature up to 500°C. Our development approach included: (a) characterizing temperature dependent carrier transport for different AlGaN HEMT heterostructures, (b) developing a suitable gate metal scheme for use in high temperatures, and (c) over-temperature testing of discrete devices and inverters. Hall mobility data revealed the GaN-channel HEMT experienced a 6.9× reduction in mobility, whereas the AlGaN channel HEMTs experienced about a 3.1x reduction. Furthermore, a greater aluminum contrast between the barrier and channel enabled higher carrier densities in the two-dimensional electron gas for all temperatures. The combination of reduced variation in mobility with temperature and high sheet carrier concentration showed that an Al-rich AlGaN-channel HEMT with a high barrier-to-channel aluminum contrast is the best option for an extreme temperature HEMT design. Three gate metal stacks were selected for low resistivity, high melting point, low thermal expansion coefficient, and high expected barrier height. The impact of thermal cycling was examined through electrical characterization of samples measured before and after rapid thermal anneal. The 200 nm tungsten gate metallization was the top performer with minimal reduction in drain current, a slightly positive threshold voltage shift, and about an order of magnitude advantage over the other gates in on-to-off current ratio. After incorporating the tungsten gate metal stack in device fabrication, characterization of transistors and inverters from room temperature up to 500°C was performed. The enhancement-mode (e-mode) devices’ resistance started increasing at about 200°C, resulting in drain current degradation. This phenomenon was not observed in depletion-mode (d-mode) devices but highlights a challenge for inverters in an e-mode driver and d-mode load configuration.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"16 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-11-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"70525905","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Ian Chin, Wei Keat Loh, Mohd Zulkifly Bin Abdullah
In this paper, a novel method for measuring hightemperature material swelling of an epoxy mold compound is explored. This work attempts to extend the swelling characterization beyond the capability of typical commercial tools. The approach uses a high-pressure chamber to maintain a saturated liquid environment for the specimen. Digital image correlation is used to measure in-situ strain change in the specimen due to hygro-thermal expansion. The results show moisture-induced swelling increases with temperature and is significant compared with thermal expansion. Results are compared against other measurement methods and published data. This has yielded good fundamental learnings for the novel concept and identified areas for future work.
{"title":"A Novel Approach for Characterizing Epoxy Mold Compound High Temperature Swelling","authors":"Ian Chin, Wei Keat Loh, Mohd Zulkifly Bin Abdullah","doi":"10.4071/001c.91225","DOIUrl":"https://doi.org/10.4071/001c.91225","url":null,"abstract":"In this paper, a novel method for measuring hightemperature material swelling of an epoxy mold compound is explored. This work attempts to extend the swelling characterization beyond the capability of typical commercial tools. The approach uses a high-pressure chamber to maintain a saturated liquid environment for the specimen. Digital image correlation is used to measure in-situ strain change in the specimen due to hygro-thermal expansion. The results show moisture-induced swelling increases with temperature and is significant compared with thermal expansion. Results are compared against other measurement methods and published data. This has yielded good fundamental learnings for the novel concept and identified areas for future work.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"213 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139325305","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this paper, we present a systematic approach for the development of application-specific antennas for 5G millimeter-wave (mmWave) base stations. First, an in-depth analysis of 5G mmWave base stations considering the required antenna gain and antenna elements to address different equivalent isotropic radiated power requirements is presented. This is followed by an evaluation of the realistic impact of different factors, which affect mmWave communication, namely output power of power amplifiers, antenna gain, losses and weather condition (rain), on transmission ranges between base station and terminals, considering the link budget analysis for an Urban Macro cell with the Non-Line-of-Sight transmission, as an example. Finally, based on a comparative analysis of published dual-band dual-polarized 5G mmWave antennas, we propose a novel configuration of a dual-band dual-polarized antenna for 5G mmWave base station applications, which overcomes the limitations of conventional antennas in published literature. Our proposed antenna covers the specified 3GHz bandwidths in the 5G mmWave n257 and n260 bands and reaches approximately 6 and 6.7 dBi, respectively in these bands. Furthermore, it exhibits at least 20 dB isolation between the polarizations and has dimensions of 1.831.83 1.2 mm. We modeled, simulated, fabricated, measured and analyzed this new antenna configuration. Excellent correlation is obtained between measurement and simulation results.
{"title":"Dual-Band Dual-Polarized Antennas for 5G mmWave Base Stations","authors":"T. H. Le, Ivan Ndip, Martin Schneider-Ramelow","doi":"10.4071/001c.91214","DOIUrl":"https://doi.org/10.4071/001c.91214","url":null,"abstract":"In this paper, we present a systematic approach for the development of application-specific antennas for 5G millimeter-wave (mmWave) base stations. First, an in-depth analysis of 5G mmWave base stations considering the required antenna gain and antenna elements to address different equivalent isotropic radiated power requirements is presented. This is followed by an evaluation of the realistic impact of different factors, which affect mmWave communication, namely output power of power amplifiers, antenna gain, losses and weather condition (rain), on transmission ranges between base station and terminals, considering the link budget analysis for an Urban Macro cell with the Non-Line-of-Sight transmission, as an example. Finally, based on a comparative analysis of published dual-band dual-polarized 5G mmWave antennas, we propose a novel configuration of a dual-band dual-polarized antenna for 5G mmWave base station applications, which overcomes the limitations of conventional antennas in published literature. Our proposed antenna covers the specified 3GHz bandwidths in the 5G mmWave n257 and n260 bands and reaches approximately 6 and 6.7 dBi, respectively in these bands. Furthermore, it exhibits at least 20 dB isolation between the polarizations and has dimensions of 1.831.83 1.2 mm. We modeled, simulated, fabricated, measured and analyzed this new antenna configuration. Excellent correlation is obtained between measurement and simulation results.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"239 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"139329673","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Conductive assembly film adhesives are extensively employed in medical, telecom, aerospace, and defense systems. Glass fabric cloth is frequently utilized as the carrier in many film adhesives to enhance handling and processability during electronic device assembly. Furthermore, practical applications have shown that film adhesives with glass fabric carriers can bond adherends with severely mismatched coefficients of thermal expansion. However, the impact of embedding glass fabric on the overall performance of assembly films has not been systematically investigated. To address this gap in knowledge, a study was conducted to compare the performance of electrically conductive film adhesives with and without the glass fabric carriers. The study focused on the mechanical performance of the film adhesives, including lap shear strength, tensile modulus, and the ability to manage applications with mismatched coefficients of thermal expansion. Additionally, the study assessed the impact of the carrier on the electrical and thermal conductivity of the film adhesives. Overall, this integrated assessment provides insights into the effectiveness of the glass fabric carrier on the performance of film adhesives.
{"title":"An Evaluation on the Mechanical and Conductive Performance of Electrically Conductive Film Adhesives with Glass Fabric Carriers","authors":"Weiyu Zhang, Yuan Zhao, Zhongwei Liu, Stone Cheng","doi":"10.4071/001c.88424","DOIUrl":"https://doi.org/10.4071/001c.88424","url":null,"abstract":"Conductive assembly film adhesives are extensively employed in medical, telecom, aerospace, and defense systems. Glass fabric cloth is frequently utilized as the carrier in many film adhesives to enhance handling and processability during electronic device assembly. Furthermore, practical applications have shown that film adhesives with glass fabric carriers can bond adherends with severely mismatched coefficients of thermal expansion. However, the impact of embedding glass fabric on the overall performance of assembly films has not been systematically investigated. To address this gap in knowledge, a study was conducted to compare the performance of electrically conductive film adhesives with and without the glass fabric carriers. The study focused on the mechanical performance of the film adhesives, including lap shear strength, tensile modulus, and the ability to manage applications with mismatched coefficients of thermal expansion. Additionally, the study assessed the impact of the carrier on the electrical and thermal conductivity of the film adhesives. Overall, this integrated assessment provides insights into the effectiveness of the glass fabric carrier on the performance of film adhesives.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"20 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135812021","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
With the advent of ultra-wide bandgap semiconductor materials, such as gallium oxide (Ga2O3) and aluminum nitride (AlN), higher temperature and higher voltage operation of power devices are becoming realizable. However, conventional polymeric and organic encapsulant materials are typically limited to operating temperatures of 200 degrees C and below. In this work, six materials were identified and evaluated as candidates for use as encapsulants for operation and high-voltage insulation at and above 250 degrees C. High-temperature silicone gel was used as a reference material and was compared with five novel encapsulants including an epoxy resin, a hydro-set cement, two low-melting point glass compounds, and a ceramic potting compound. Gas pycnometry was utilized to evaluate the voiding concentration to avoid partial discharge. Each material was then processed onto a direct-bonded-aluminum substrate test coupon to evaluate compatibility with a commonly used metal-ceramic substrate and processability for use in a power module. The insulation capability of each material was evaluated by testing the partial discharge inception voltage (PDIV) across a 1-mm gap etched in the substrate. The dielectric stability was then tested by soaking the materials in air at 250 degrees C for various intervals and observing the degradation of their PDIVs and appearances. The results of each test were compared, and conclusions were drawn about each material’s feasibility for use as a dielectric encapsulation material for a power module operating at temperatures exceeding 200 degrees C.
{"title":"Investigation and Evaluation of High-Temperature Encapsulation Materials for Power Module Applications","authors":"Benjamin Lyon, Christina DiMarino","doi":"10.4071/001c.88421","DOIUrl":"https://doi.org/10.4071/001c.88421","url":null,"abstract":"With the advent of ultra-wide bandgap semiconductor materials, such as gallium oxide (Ga2O3) and aluminum nitride (AlN), higher temperature and higher voltage operation of power devices are becoming realizable. However, conventional polymeric and organic encapsulant materials are typically limited to operating temperatures of 200 degrees C and below. In this work, six materials were identified and evaluated as candidates for use as encapsulants for operation and high-voltage insulation at and above 250 degrees C. High-temperature silicone gel was used as a reference material and was compared with five novel encapsulants including an epoxy resin, a hydro-set cement, two low-melting point glass compounds, and a ceramic potting compound. Gas pycnometry was utilized to evaluate the voiding concentration to avoid partial discharge. Each material was then processed onto a direct-bonded-aluminum substrate test coupon to evaluate compatibility with a commonly used metal-ceramic substrate and processability for use in a power module. The insulation capability of each material was evaluated by testing the partial discharge inception voltage (PDIV) across a 1-mm gap etched in the substrate. The dielectric stability was then tested by soaking the materials in air at 250 degrees C for various intervals and observing the degradation of their PDIVs and appearances. The results of each test were compared, and conclusions were drawn about each material’s feasibility for use as a dielectric encapsulation material for a power module operating at temperatures exceeding 200 degrees C.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"54 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135812025","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Yuan Zhao, Bruno Tolla, Doug Katze, Glenda Castaneda, Jo-Anne Wilson, David Brand
Aerospace and defense applications present unique challenges for material suppliers. As increasing adoption of advanced semiconductor materials and Diverse Accessible Heterogeneous Integration technologies, power density of defense and aerospace devices increases rapidly. Traditional die-attaching technology is becoming an increasingly limiting factor in microelectronics packaging for the next generation aerospace and defense systems. Metal particle sintering creates a porous metal foam, which can significantly enhance heat transfer within the sintered material. However, the traditional silver sintering requires very high sintering temperatures that cannot be tolerated by typical microelectronics devices. In addition, the sintered metal foam contains open-cell pores that can absorb/entrap moisture and dusts, which poses a reliability risk. This article introduces an advanced hybrid silver sintering material, which incorporates highperformance silver sintering with high reliability and process-friendly of epoxy-based die-attaching technology. This hybrid sintering paste can be processed without applying any pressures in temperature ranges that are normal in microelectronics packaging processes. Preliminary experimental studies, including Scanning Electron Microscopic study, volume resistivity tests, die shear strength tests, and thermal resistance tests, were performed for developing a low temperature sintering schedule that is compatible with normal assembly processes of high-power density electronics devices. The results indicated that the hybrid material could achieve silver sintering at 150 degrees C and offer 36 enhancement on thermal performance comparing with a widely used die-attach material.
{"title":"A Hybrid Pressureless Silver Sintering Technology for High-Power Density Electronics","authors":"Yuan Zhao, Bruno Tolla, Doug Katze, Glenda Castaneda, Jo-Anne Wilson, David Brand","doi":"10.4071/001c.88422","DOIUrl":"https://doi.org/10.4071/001c.88422","url":null,"abstract":"Aerospace and defense applications present unique challenges for material suppliers. As increasing adoption of advanced semiconductor materials and Diverse Accessible Heterogeneous Integration technologies, power density of defense and aerospace devices increases rapidly. Traditional die-attaching technology is becoming an increasingly limiting factor in microelectronics packaging for the next generation aerospace and defense systems. Metal particle sintering creates a porous metal foam, which can significantly enhance heat transfer within the sintered material. However, the traditional silver sintering requires very high sintering temperatures that cannot be tolerated by typical microelectronics devices. In addition, the sintered metal foam contains open-cell pores that can absorb/entrap moisture and dusts, which poses a reliability risk. This article introduces an advanced hybrid silver sintering material, which incorporates highperformance silver sintering with high reliability and process-friendly of epoxy-based die-attaching technology. This hybrid sintering paste can be processed without applying any pressures in temperature ranges that are normal in microelectronics packaging processes. Preliminary experimental studies, including Scanning Electron Microscopic study, volume resistivity tests, die shear strength tests, and thermal resistance tests, were performed for developing a low temperature sintering schedule that is compatible with normal assembly processes of high-power density electronics devices. The results indicated that the hybrid material could achieve silver sintering at 150 degrees C and offer 36 enhancement on thermal performance comparing with a widely used die-attach material.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"36 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-07-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135812024","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Sourish S. Sinha, Tzu-Hsuan Cheng, Douglas C. Hopkins
Wide Bandgap devices (WBG) have led to an era of high-speed and high-voltage operations that were not previously achievable with silicon devices. However, packaging these devices in the power module has been a challenge due to higher switching rates, which can cause several amperes of displacement current to flow through the parasitic capacitance of the package, thus impacting the gate driver operation and the switching ability of the device. The severity of this current increases in thin packaging substrates, unlike the traditional inorganic substrates, e.g., Direct Bond Copper (DBC) and thus, a thorough investigation is needed before it can be used with WBG semiconductors. The objective of this article is to discuss ways to reduce as well as manipulate the parasitic capacitance at different locations in the power modules to reduce the magnitude of the peak and Root Mean Square (RMS ) value of the displacement current and have a better gate drive signal and power waveform. To study this, a Double Pulse Test (DPT) simulation study has been conducted to show how an intelligent distribution of parasitic capacitance benefits the device functioning. This has been validated through experimental fabrication and DPT of dense power module following proposed guidelines. A detailed description of the design of a high-speed capable DPT circuit and measurement setup has been specified to show the steps needed for reliable testing and measurement.
{"title":"Double-Sided Integrated GaN Power Module with Double Pulse Test (DPT) Verification","authors":"Sourish S. Sinha, Tzu-Hsuan Cheng, Douglas C. Hopkins","doi":"10.4071/001c.81980","DOIUrl":"https://doi.org/10.4071/001c.81980","url":null,"abstract":"Wide Bandgap devices (WBG) have led to an era of high-speed and high-voltage operations that were not previously achievable with silicon devices. However, packaging these devices in the power module has been a challenge due to higher switching rates, which can cause several amperes of displacement current to flow through the parasitic capacitance of the package, thus impacting the gate driver operation and the switching ability of the device. The severity of this current increases in thin packaging substrates, unlike the traditional inorganic substrates, e.g., Direct Bond Copper (DBC) and thus, a thorough investigation is needed before it can be used with WBG semiconductors. The objective of this article is to discuss ways to reduce as well as manipulate the parasitic capacitance at different locations in the power modules to reduce the magnitude of the peak and Root Mean Square (RMS ) value of the displacement current and have a better gate drive signal and power waveform. To study this, a Double Pulse Test (DPT) simulation study has been conducted to show how an intelligent distribution of parasitic capacitance benefits the device functioning. This has been validated through experimental fabrication and DPT of dense power module following proposed guidelines. A detailed description of the design of a high-speed capable DPT circuit and measurement setup has been specified to show the steps needed for reliable testing and measurement.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"38 1","pages":"0"},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"135672139","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Thermomechanical stress generation on a silicon chip in an embedded-die package (EDP) was investigated. Change in thermomechanical stress on the chip with temperature was evaluated using piezo-resistance gauges fabricated on the chip. To investigate the impact of a redistribution layer (RDL) on stress generation, an EDP where filling materials facing the top and bottom sides and the periphery of the embedded die were entirely removed was fabricated. The removal of filling materials was carried out by using the CO2 laser ablation technology. RDL having diagonal paths from the substrate to the chip was designed and fabricated in addition to the conventional orthogonal RDL. RDLs were made of copper. Temperature tests were carried out in the range from 260 degrees C to 100 degrees C. The experimental results indicate that, while the origin of thermomechanical stress is a mismatch in coefficients of thermal expansion (CTE) between the chip and the organic substrate, RDL plays a significant role in generating the thermomechanical stress on the chip. The results also show that the diagonal RDL design effectively reduces thermomechanical stress from the orthogonal RDL design owing to its spring characteristic.
{"title":"Investigation into Impact of Redistribution Layer Design on Thermomechanical Stress in Embedded-Die Package","authors":"M. Matsuura, T. Asano, H. Kanaya","doi":"10.4071/001c.81979","DOIUrl":"https://doi.org/10.4071/001c.81979","url":null,"abstract":"Thermomechanical stress generation on a silicon chip in an embedded-die package (EDP) was investigated. Change in thermomechanical stress on the chip with temperature was evaluated using piezo-resistance gauges fabricated on the chip. To investigate the impact of a redistribution layer (RDL) on stress generation, an EDP where filling materials facing the top and bottom sides and the periphery of the embedded die were entirely removed was fabricated. The removal of filling materials was carried out by using the CO2 laser ablation technology. RDL having diagonal paths from the substrate to the chip was designed and fabricated in addition to the conventional orthogonal RDL. RDLs were made of copper. Temperature tests were carried out in the range from 260 degrees C to 100 degrees C. The experimental results indicate that, while the origin of thermomechanical stress is a mismatch in coefficients of thermal expansion (CTE) between the chip and the organic substrate, RDL plays a significant role in generating the thermomechanical stress on the chip. The results also show that the diagonal RDL design effectively reduces thermomechanical stress from the orthogonal RDL design owing to its spring characteristic.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":"1 1","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"42576795","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
In this study, the recent advances and trends in chiplet lateral communications (bridges) will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of chiplet horizontal communications. Some recommendations will also be provided.
{"title":"State-of-the-Art in Chiplets Horizontal Communications","authors":"J. Lau","doi":"10.4071/001c.81977","DOIUrl":"https://doi.org/10.4071/001c.81977","url":null,"abstract":"In this study, the recent advances and trends in chiplet lateral communications (bridges) will be investigated. Emphasis is placed on the definition, kinds, advantages and disadvantages, challenges (opportunities), and examples of chiplet horizontal communications. Some recommendations will also be provided.","PeriodicalId":35312,"journal":{"name":"Journal of Microelectronics and Electronic Packaging","volume":" ","pages":""},"PeriodicalIF":0.0,"publicationDate":"2023-04-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"47833537","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
京公网安备 11010802042870号
京ICP备2023020795号-1
扫码关注我们
求助内容：
应助结果提醒方式：