Analyzing the impact of parasitics on a CMOS-Memristive crossbar neural network based on winner-take-all and Hebbian rule

Sherin A. Thomas , Rohit Sharma , Devarshi Mrinal Das
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Abstract

For cognitive tasks and classifications, neuromorphic systems have shown great potential. This paper presents a novel architecture using CMOS memristive synapses where the memristors are trained using the Hebbian rule, and the winner-take-all mechanism is used for the recognition task. The proposed architecture offers a simplified approach compared to previous state-of-the-art works, making it accessible for implementing pattern recognition tasks with in-memory computation. As the size of the memristive switching devices is in the nanometer scale, designing, modeling, and optimizing the system becomes increasingly complex. This complexity leads to various signal integrity issues that arise due to parasitic components of the crossbar. A crossbar array architecture is designed using the extracted crossbar’s parasitic components obtained using the Q3D extractor. The modeled architecture provides insight into the crossbar array’s parasitic affect behavior at the schematic level for different real-time applications and how the parasitics of the crossbar will affect the fidelity and performance of the system. The proposed architecture uses a threshold-based post-synaptic neuron, which does not require any capacitor, unlike the LIF neuron, and occupies a smaller area. A neuron refractory controller is designed to make the training process efficient by keeping track of the neuron already fired and preventing it from firing in the consecutive training phase. The CMOS memristive synapse uses an average of 0.32 nJ energy to recognize each pattern, much less than earlier works. The proposed architecture is validated using 180 nm CMOS technology.

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基于赢者通吃和Hebbian规则的CMOS忆阻交叉神经网络寄生效应分析
对于认知任务和分类,神经形态系统已经显示出巨大的潜力。本文提出了一种使用CMOS忆阻突触的新架构,其中忆阻器使用Hebbian规则进行训练,并且赢家通吃机制用于识别任务。与以前最先进的工作相比,所提出的体系结构提供了一种简化的方法,使其能够通过内存计算实现模式识别任务。随着忆阻开关器件的尺寸达到纳米级,系统的设计、建模和优化变得越来越复杂。这种复杂性导致由于交叉开关的寄生组件而出现的各种信号完整性问题。使用使用Q3D提取器获得的所提取的交叉开关的寄生分量来设计交叉开关阵列架构。建模的体系结构在不同实时应用的示意图级别上深入了解了交叉开关阵列的寄生影响行为,以及交叉开关的寄生将如何影响系统的保真度和性能。所提出的架构使用基于阈值的突触后神经元,与LIF神经元不同,该神经元不需要任何电容器,并且占用较小的面积。设计了一种神经元难熔控制器,通过跟踪已经激发的神经元并防止其在连续训练阶段激发,使训练过程高效。CMOS忆阻突触平均使用0.32nJ的能量来识别每个模式,比早期的工作要少得多。使用180nm CMOS技术对所提出的架构进行了验证。
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