Sn Bumping Without Photoresist Mould and Si Dice Stacking for 3-D Packaging

Sung-Jun Hong, Ji Heon Jun, J. Jung, M. Mayer, Yujie Zhou
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引用次数: 14

Abstract

Chip stacking with through-silicon-vias (TSV) technology for 3-D packaging of electronic devices was investigated. A new process of direct solder bumping on Si wafers without photoresist (PR) mould was designed and applied in this study. The Cu extrusion process on the via was also omitted for process simplification. This simplified process can be useful for cost reduction and increased productivity. The substrate for the experiments was a p-type 〈100 〉 Si wafer of 100 mm diameter. In order to produce the vias, the Si wafer was etched by a deep reactive ion etcher (DRIE) using SF6 and C4F8 plasmas alternately. The produced vias were 40 μm in diameter and 80 μm in depth. On the via side walls, SiO2, Ti, and Au layers were formed with thicknesses of 1, 0.1, and 0.7μm, respectively. Pulsed direct current (DC) electroplating was used to fill the vias with Cu. Then the Si wafer was back ground to a thickness of 80 μm until the Cu filling in the vias was exposed to the surface without extrusion. Plating current subsequently flowed through the vias to the bumping surface, and Sn was electroplated on the Cu filling directly without a PR mould. To optimize the bumping process, the current density and time for Sn plating were varied from 0.04 to 0.06 A/cm2 and from 10 to 40 min, respectively. Bumps with a height of 20 μm were formed successfully with 0.05 A/cm2 and 30 min without a PR mould. The bump height increased with increasing plating current and time; for example, from 13 μm at 10 min to 33 μm at 40 min in case of 0.06 A/cm2. The Si dice with electroplated Sn bumps had dimensions of 5 × 5 mm and thickness of 80 μm. Three Si dice were stacked successfully by micro-soldering at 260°C. In the interface between the Sn bumps and the Cu filling, a Cu6Sn5 intermetallic compound was produced with a thickness of 3.2 μm. Through this study, a process for non-PR solder bumping by electroplating and wafer stacking with TSV was achieved successfully.
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无光刻胶模具的锡碰撞和三维包装的硅片堆积
研究了用于电子器件三维封装的硅通孔(TSV)芯片堆叠技术。设计并应用了一种无需光刻胶(PR)模具直接在硅片上碰撞焊料的新工艺。为简化工艺,省去了铜在通孔上的挤压工艺。这个简化的过程对于降低成本和提高生产率非常有用。实验的衬底为直径为100 mm的p型< 100 > Si晶片。为了制造通孔,用深反应离子蚀刻机(DRIE)交替使用SF6和C4F8等离子体蚀刻硅晶片。所生产的通孔直径为40 μm,深度为80 μm。在通孔侧壁形成厚度分别为1 μm、0.1 μm和0.7μm的SiO2、Ti和Au层。采用脉冲直流(DC)电镀方法在孔内填充Cu。然后将硅片回磨至80 μm厚度,直至孔内的Cu填充物不挤压暴露在表面。电镀电流随后通过通孔流到碰撞表面,无需PR模具直接将Sn电镀在Cu填料上。电镀锡的电流密度为0.04 ~ 0.06 A/cm2,电镀锡的时间为10 ~ 40 min。在不使用PR模具的情况下,以0.05 a /cm2和30 min的速度成功地形成了高度为20 μm的凸起。随着电镀电流的增大和电镀时间的延长,凸起高度增大;例如,在0.06 A/cm2的情况下,从10分钟的13 μm到40分钟的33 μm。电镀锡凸点的Si片尺寸为5 × 5 mm,厚度为80 μm。在260°C的温度下,通过微焊接成功地堆叠了3块硅片。在Sn凸起与Cu填充物的界面上,形成了厚度为3.2 μm的Cu6Sn5金属间化合物。通过本研究,成功地实现了一种用TSV电镀和堆垛的非pr焊料碰撞工艺。
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来源期刊
IEEE Transactions on Advanced Packaging
IEEE Transactions on Advanced Packaging 工程技术-材料科学:综合
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审稿时长
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