{"title":"A 19–34-GHz Bridged-T Phase Shifter With High-Pass Phase Compensation Achieving 3.9° RMS Phase Error for 5G NR","authors":"Yijing Liao;Minzhe Tang;Jian Pang;Atsushi Shirane;Kenichi Okada","doi":"10.1109/LSSC.2023.3305832","DOIUrl":null,"url":null,"abstract":"This letter presents a 4-bit switch-type phase shifter (STPS) with low phase error using standard 65-nm bulk CMOS technology. To reduce the phase error of conventional STPS, the proposed design employs a phase compensation network, utilizing opposite phase-shift characteristics of different filters. The measured maximum root-mean-square (RMS) phase and gain errors are 3.9° and 2.2 dB from 19 to 34 GHz, respectively. The measured RMS group delay error is smaller than 3.8 ps within the operating frequencies. The core area of the fabricated phase shifter is \n<inline-formula> <tex-math>${0.13 \\mathrm {mm}}^{2}$ </tex-math></inline-formula>\n excluding pads. The proposed phase shifter performs a low phase error with compact chip size compared with other reported STPSs within a similar bandwidth.","PeriodicalId":13032,"journal":{"name":"IEEE Solid-State Circuits Letters","volume":null,"pages":null},"PeriodicalIF":2.2000,"publicationDate":"2023-08-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE Solid-State Circuits Letters","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/10220238/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q3","JCRName":"COMPUTER SCIENCE, HARDWARE & ARCHITECTURE","Score":null,"Total":0}
引用次数: 1
Abstract
This letter presents a 4-bit switch-type phase shifter (STPS) with low phase error using standard 65-nm bulk CMOS technology. To reduce the phase error of conventional STPS, the proposed design employs a phase compensation network, utilizing opposite phase-shift characteristics of different filters. The measured maximum root-mean-square (RMS) phase and gain errors are 3.9° and 2.2 dB from 19 to 34 GHz, respectively. The measured RMS group delay error is smaller than 3.8 ps within the operating frequencies. The core area of the fabricated phase shifter is
${0.13 \mathrm {mm}}^{2}$
excluding pads. The proposed phase shifter performs a low phase error with compact chip size compared with other reported STPSs within a similar bandwidth.