Mohammad Emami Meybodi;Hector Gomez;Yu-Chun Lu;Hossein Shakiba;Ali Sheikholeslami
{"title":"Design and Implementation of an On-Demand Maximum-Likelihood Sequence Estimation (MLSE)","authors":"Mohammad Emami Meybodi;Hector Gomez;Yu-Chun Lu;Hossein Shakiba;Ali Sheikholeslami","doi":"10.1109/OJCAS.2022.3173686","DOIUrl":null,"url":null,"abstract":"This paper proposes a novel design for Maximum Likelihood Sequence Estimation (MLSE) used in ultra-high-speed wireline communication. We take advantage of the propagated errors caused by Decision-Feedback Equalizer (DFE) to activate and guide the MLSE, thereby reducing its complexity. The design is customized for a 4-PAM, 1 + D signaling system, and synthesized in 16nm FinFET TSMC Technology. For comparison purposes, a conventional MLSE is also synthesized in the same technology. The synthesis report confirms that the proposed design consumes 1/10 of the power and occupies 1/15 of the area required by the conventional MLSE while having a comparable bit error rate.","PeriodicalId":93442,"journal":{"name":"IEEE open journal of circuits and systems","volume":null,"pages":null},"PeriodicalIF":2.4000,"publicationDate":"2022-03-11","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=9772752","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE open journal of circuits and systems","FirstCategoryId":"1085","ListUrlMain":"https://ieeexplore.ieee.org/document/9772752/","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"Q2","JCRName":"ENGINEERING, ELECTRICAL & ELECTRONIC","Score":null,"Total":0}
引用次数: 3
Abstract
This paper proposes a novel design for Maximum Likelihood Sequence Estimation (MLSE) used in ultra-high-speed wireline communication. We take advantage of the propagated errors caused by Decision-Feedback Equalizer (DFE) to activate and guide the MLSE, thereby reducing its complexity. The design is customized for a 4-PAM, 1 + D signaling system, and synthesized in 16nm FinFET TSMC Technology. For comparison purposes, a conventional MLSE is also synthesized in the same technology. The synthesis report confirms that the proposed design consumes 1/10 of the power and occupies 1/15 of the area required by the conventional MLSE while having a comparable bit error rate.