R. Gusmeroli, A. Spinelli, C. M. Compagnoni, D. Ielmini, A. Lacaita
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引用次数: 1
Abstract
Among the new memory concepts proposed in the last decade to replace the conventional flash cell, nanocrystal memories received large attentions because of their simple and CMOS compatible process flow. Using a 3-dimensional Monte Carlo simulator, we investigated the scaling perspectives of the nanocrystal memory technology due to reliability constraints. Results show that scaling this technology beyond the 45 nm node will drastically reduce the benefits deriving from distributed floating-gate effects and increase the program fail probability
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