Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644014
V. Obreja, C. Codreanu
Due to high level of the leakage reverse current, commercial power silicon diodes available at this time have no specification in the data sheets for operation above 200 degC junction temperature. An experimental method is presented to extract information about the uniformity of the reverse current flow over the silicon die area. The power diode with copper attached heat sink is placed in a hot chamber where the temperature is set, so that the level of reverse current to be enough for heat generation. For the same applied power dissipation at reverse and forward bias, the additional junction temperature increase is monitored by the level of reverse current or by the level of the forward current at constant voltage. Experiments have been performed on commercial silicon diode samples in metallic package. It has been found that the additional junction temperature increase is significantly different, when the same power dissipation is applied at reverse bias and then at forward bias voltage, with the device placed in hot chamber at 200degC or 250 degC, depending on the current level
{"title":"Experimental Investigation on the Leakage Reverse Current Component Flowing at the Semiconductor PN Junction Periphery","authors":"V. Obreja, C. Codreanu","doi":"10.1109/ESIME.2006.1644014","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644014","url":null,"abstract":"Due to high level of the leakage reverse current, commercial power silicon diodes available at this time have no specification in the data sheets for operation above 200 degC junction temperature. An experimental method is presented to extract information about the uniformity of the reverse current flow over the silicon die area. The power diode with copper attached heat sink is placed in a hot chamber where the temperature is set, so that the level of reverse current to be enough for heat generation. For the same applied power dissipation at reverse and forward bias, the additional junction temperature increase is monitored by the level of reverse current or by the level of the forward current at constant voltage. Experiments have been performed on commercial silicon diode samples in metallic package. It has been found that the additional junction temperature increase is significantly different, when the same power dissipation is applied at reverse bias and then at forward bias voltage, with the device placed in hot chamber at 200degC or 250 degC, depending on the current level","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73530312","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643975
Bice Chini, Joseph W. Jerome, Riccardo Sacco
This communication deals with the mathematical modeling and numerical simulation of charge transport in single-cell ionic channels. The adopted model consists of a coupled system comprising the Poisson-Nernst-Planck and the Navier-Stokes equations. Suitable functional iteration techniques are used to successively solve the model equations, and stable and conservative finite element methods are employed for the discretization of each linearized problem arising from decoupling. Models and computational techniques are validated on the numerical simulation of a two-dimensional ionic channel under several working conditions
{"title":"Multi-Physics Modeling and Finite Element Approximation of Charge Flow in Ionic Channels","authors":"Bice Chini, Joseph W. Jerome, Riccardo Sacco","doi":"10.1109/ESIME.2006.1643975","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643975","url":null,"abstract":"This communication deals with the mathematical modeling and numerical simulation of charge transport in single-cell ionic channels. The adopted model consists of a coupled system comprising the Poisson-Nernst-Planck and the Navier-Stokes equations. Suitable functional iteration techniques are used to successively solve the model equations, and stable and conservative finite element methods are employed for the discretization of each linearized problem arising from decoupling. Models and computational techniques are validated on the numerical simulation of a two-dimensional ionic channel under several working conditions","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73059120","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644013
W. V. van Driel, A. Grech, T. Hauck, I. Schmadlak, X. Zhang, S. Orain
The continuous industry drive for miniaturization and function integration forces the development of feature sizes down to the nanometer regime. Although the industry has just solved the major problems in CMOS090 technology, a new hurdle is to be taken: CMOS065. And again, new materials will be introduced. Black Diamond-I, used in CMOS090, will be replaced by Black Diamond-II(x). This new material is porous and, thus, not being a homogeneous material any more. For sure that this will have major impacts on the thermomechanical performance of the total IC stack. The problems encountered during CMOS090 at least showed that IC and package reliability (and PCB?) are strongly interacted. Finite element techniques are widely used to predict the deformations and stresses and their evolution during IC processes, packaging manufacturing processes and/or product testing. Modeling techniques such as contact elements, global-local, sub-structuring, element birth and death and material models such as fracture mechanics, visco-elasticity, plasticity and creep are rapidly developed to predict the stress and strain state in the electronic package. Still, experiments are necessary to verify the calculated results in order to be sure that the results obtained from FE models are reliable and accurate enough from both quantitative and qualitative perspective. No doubt that to first-time-right develop CMOS065 and beyond will require the use of combined state-of-the-art modeling and experimental techniques. It will enable the industry not only to predict thermo-mechanically induced failures in electronic packages in early stages, but also to understand the precise failure mechanisms involved. To strengthen the development, the Crolles2 Alliance was founded between the industry leaders STMicroelectronics, Philips, and Freescale. As part of the Alliance, the CAA Modeling Cooperation, consisting of the representatives of each companies modeling team started to assist the 65-node development with state-of-the-art virtual prototyping techniques. This paper highlights the major research and development results of that cooperation so far
工业对小型化和功能集成的持续推动迫使特征尺寸的发展下降到纳米级别。虽然业界刚刚解决了CMOS090技术的主要问题，但一个新的障碍是要采取:CMOS065。同样，新材料也会被引入。CMOS090中使用的黑金刚石- i将被黑金刚石- ii (x)所取代。这种新材料是多孔的，因此不再是一种均匀的材料。可以肯定的是，这将对整个集成电路堆栈的热力学性能产生重大影响。在CMOS090期间遇到的问题至少表明IC和封装可靠性(以及PCB?)是强烈相互作用的。有限元技术被广泛用于预测集成电路过程、封装制造过程和/或产品测试过程中的变形和应力及其演变。接触单元、整体-局部、子结构、单元生灭等建模技术和断裂力学、粘弹性、塑性和蠕变等材料模型迅速发展，用于预测电子封装内部的应力和应变状态。然而，为了从定量和定性的角度确保有限元模型得到的结果足够可靠和准确，还需要进行实验来验证计算结果。毫无疑问，要首次正确开发CMOS065及以后的产品，将需要使用最先进的建模和实验技术相结合。这将使行业不仅能够在早期阶段预测电子封装中热机械引起的故障，而且还可以了解所涉及的精确故障机制。为了加强发展，业界领袖意法半导体、飞利浦和飞思卡尔之间成立了Crolles2联盟。作为联盟的一部分，由每个公司建模团队的代表组成的CAA建模合作组织开始用最先进的虚拟原型技术协助65节点的开发。本文重点介绍了该合作迄今取得的主要研发成果
{"title":"Virtual Prototyping based Design Optimization of the Substrate, Leadframe, and Flip Chip Package Families with Low-k Technology","authors":"W. V. van Driel, A. Grech, T. Hauck, I. Schmadlak, X. Zhang, S. Orain","doi":"10.1109/ESIME.2006.1644013","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644013","url":null,"abstract":"The continuous industry drive for miniaturization and function integration forces the development of feature sizes down to the nanometer regime. Although the industry has just solved the major problems in CMOS090 technology, a new hurdle is to be taken: CMOS065. And again, new materials will be introduced. Black Diamond-I, used in CMOS090, will be replaced by Black Diamond-II(x). This new material is porous and, thus, not being a homogeneous material any more. For sure that this will have major impacts on the thermomechanical performance of the total IC stack. The problems encountered during CMOS090 at least showed that IC and package reliability (and PCB?) are strongly interacted. Finite element techniques are widely used to predict the deformations and stresses and their evolution during IC processes, packaging manufacturing processes and/or product testing. Modeling techniques such as contact elements, global-local, sub-structuring, element birth and death and material models such as fracture mechanics, visco-elasticity, plasticity and creep are rapidly developed to predict the stress and strain state in the electronic package. Still, experiments are necessary to verify the calculated results in order to be sure that the results obtained from FE models are reliable and accurate enough from both quantitative and qualitative perspective. No doubt that to first-time-right develop CMOS065 and beyond will require the use of combined state-of-the-art modeling and experimental techniques. It will enable the industry not only to predict thermo-mechanically induced failures in electronic packages in early stages, but also to understand the precise failure mechanisms involved. To strengthen the development, the Crolles2 Alliance was founded between the industry leaders STMicroelectronics, Philips, and Freescale. As part of the Alliance, the CAA Modeling Cooperation, consisting of the representatives of each companies modeling team started to assist the 65-node development with state-of-the-art virtual prototyping techniques. This paper highlights the major research and development results of that cooperation so far","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75364863","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643967
M. Yew, C. Yuan, K. Chiang, Yu-Hua Chen, Wen-Kung Yang
As electronic devices become more complicated and the need for semiconductor chips in portable products increases, the demand for smaller and lighter chips and packages becomes greater. However, because of the different temperature loading from the manufacturing process, the mismatch in the coefficient of thermal expansion (CTE) between different materials affects the packaging reliability. In this study, the chip-in-substrate package (CiSP), which has been developed by ITRI/ERSO and Fraunhofer IZM, is chosen as the test instrument. For the purpose of comprehending the stress/strain accumulation during the manufacturing process, a process modeling methodology has been executed to determine the evolution of stresses distribution during the sequential fabrication of CiSP structures. In addition, to further improve the packaging design of CiSP, the stress/strain variation around the most critical region is investigated by means of the design of experiment (DOE). A two-step design method based on the validated model is proposed for the development of the CiSP. The analytic results reveal that decreasing the thickness of the lamination layer and increasing the thickness of the interconnect can effectively reduce the stress concentration phenomenon. The robust design parameters for the CiSP could be achieved through the analytical procedures presented in this study. Therefore, the CiSP can be fabricated within the validated design parameters and can consequently meet the demand of decreasing the amount of time involved in product development
{"title":"Sensitivity Design of the Chip-in-Substrate Package Using DOE with Factorial Analysis Technology","authors":"M. Yew, C. Yuan, K. Chiang, Yu-Hua Chen, Wen-Kung Yang","doi":"10.1109/ESIME.2006.1643967","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643967","url":null,"abstract":"As electronic devices become more complicated and the need for semiconductor chips in portable products increases, the demand for smaller and lighter chips and packages becomes greater. However, because of the different temperature loading from the manufacturing process, the mismatch in the coefficient of thermal expansion (CTE) between different materials affects the packaging reliability. In this study, the chip-in-substrate package (CiSP), which has been developed by ITRI/ERSO and Fraunhofer IZM, is chosen as the test instrument. For the purpose of comprehending the stress/strain accumulation during the manufacturing process, a process modeling methodology has been executed to determine the evolution of stresses distribution during the sequential fabrication of CiSP structures. In addition, to further improve the packaging design of CiSP, the stress/strain variation around the most critical region is investigated by means of the design of experiment (DOE). A two-step design method based on the validated model is proposed for the development of the CiSP. The analytic results reveal that decreasing the thickness of the lamination layer and increasing the thickness of the interconnect can effectively reduce the stress concentration phenomenon. The robust design parameters for the CiSP could be achieved through the analytical procedures presented in this study. Therefore, the CiSP can be fabricated within the validated design parameters and can consequently meet the demand of decreasing the amount of time involved in product development","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74109817","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644015
M. Meuwissen, A. E. Van der Waal, I. Hovens, C. Rentrop
This paper describes work carried out as part of a larger project aimed at the development of nanosized particle filled underfill material. Several characterisation experiments have been applied to study the influence of these particles on the curing behaviour and the thermomechanical properties such as the coefficient of thermal expansion, geltime, glass transition temperature, and modulus. Constitutive models are assessed for their ability to describe the observed behaviour
{"title":"Thermo-mechanical characterisation of a nanosized particle filled underfill","authors":"M. Meuwissen, A. E. Van der Waal, I. Hovens, C. Rentrop","doi":"10.1109/ESIME.2006.1644015","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644015","url":null,"abstract":"This paper describes work carried out as part of a larger project aimed at the development of nanosized particle filled underfill material. Several characterisation experiments have been applied to study the influence of these particles on the curing behaviour and the thermomechanical properties such as the coefficient of thermal expansion, geltime, glass transition temperature, and modulus. Constitutive models are assessed for their ability to describe the observed behaviour","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1109/ESIME.2006.1644015","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72530963","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643987
J. Beijer, M. Jansen, G. Janssen, J. Bielen, E. Tijssen
Usually the mechanical reliability of electronic packages is qualified by temperature cycle tests (TCT). However this is a more or less isothermal test, while in operating condition temperatures can have a non-uniform distribution, because thermal transient effects are present. This effect can play an important role in packages that generate heat, like the module with power amplifier that we studied in this work. The transient thermal loading in the active areas in the flip chip power amplifier causes thermo-mechanical stresses that may cause fatigue fractures in the solder bumps and eventually failure of the module. In this paper we simulate the operating conditions and a TCT. For this purpose a FEA model was created with a new way of working to handle major challenges regarding the large differences in length and time scale. The required element size in the bumps was approximately a factor 200 smaller than that required in the PCB. Furthermore the combination of the heat penetration depth of the short (milliseconds) power pulses together with the heating time of approximately half an hour for the complete module makes conventional simulation methods very time consuming. The new method showed to be accurate and efficient. The simulation results show that in TCT the loading is very different than in power cycling. The critical bump was in power cycling in the middle of the heating area, while in TCT is located at the corner. We have also calculated an acceleration factor for the TCT test
{"title":"Fatigue life of solder bumps in a system in package: relating power cycling to thermal cycling","authors":"J. Beijer, M. Jansen, G. Janssen, J. Bielen, E. Tijssen","doi":"10.1109/ESIME.2006.1643987","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643987","url":null,"abstract":"Usually the mechanical reliability of electronic packages is qualified by temperature cycle tests (TCT). However this is a more or less isothermal test, while in operating condition temperatures can have a non-uniform distribution, because thermal transient effects are present. This effect can play an important role in packages that generate heat, like the module with power amplifier that we studied in this work. The transient thermal loading in the active areas in the flip chip power amplifier causes thermo-mechanical stresses that may cause fatigue fractures in the solder bumps and eventually failure of the module. In this paper we simulate the operating conditions and a TCT. For this purpose a FEA model was created with a new way of working to handle major challenges regarding the large differences in length and time scale. The required element size in the bumps was approximately a factor 200 smaller than that required in the PCB. Furthermore the combination of the heat penetration depth of the short (milliseconds) power pulses together with the heating time of approximately half an hour for the complete module makes conventional simulation methods very time consuming. The new method showed to be accurate and efficient. The simulation results show that in TCT the loading is very different than in power cycling. The critical bump was in power cycling in the middle of the heating area, while in TCT is located at the corner. We have also calculated an acceleration factor for the TCT test","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80281881","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1644047
R. Mukhiya, A. Adami, A. Bagolini, M. Zen, S. Kal
This paper reports the design and simulation of two MEMS piezoresistive accelerometers for single axis low g (plusmn2g) automotive applications. Both the accelerometer structures consist of four beams at the top with eight embedded resistors as sensing elements to form Wheatstone bridge network and interconnected to minimize the cross axis sensitivity. FEM based design and simulation results for both the accelerometers are presented and compared, which are performed using commercially available MEMSCAD tool CoventorWarereg. Fabrication process and technological aspects to realize both the structures are discussed. The sensitivity of the two accelerometers is 6.5 mV/g and 5.85 mV/g respectively. Cross axis sensitivity of the structures is three orders lower than the prime axis sensitivity
{"title":"FEM Based Design and Simulation of Bulk Micromachined MEMS Accelerometers with Low Cross Axis Sensitivity","authors":"R. Mukhiya, A. Adami, A. Bagolini, M. Zen, S. Kal","doi":"10.1109/ESIME.2006.1644047","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1644047","url":null,"abstract":"This paper reports the design and simulation of two MEMS piezoresistive accelerometers for single axis low g (plusmn2g) automotive applications. Both the accelerometer structures consist of four beams at the top with eight embedded resistors as sensing elements to form Wheatstone bridge network and interconnected to minimize the cross axis sensitivity. FEM based design and simulation results for both the accelerometers are presented and compared, which are performed using commercially available MEMSCAD tool CoventorWarereg. Fabrication process and technological aspects to realize both the structures are discussed. The sensitivity of the two accelerometers is 6.5 mV/g and 5.85 mV/g respectively. Cross axis sensitivity of the structures is three orders lower than the prime axis sensitivity","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"78995701","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2006-04-24DOI: 10.1109/ESIME.2006.1643970
C. Yuan, G.Q. Zhang, Ching-Shun Huang, Chun-Hui Yu, Chin-Cheng Yang, Wen-Kung Yang, M. Yew, C. Chou, K. Chiang
A novel wafer level chip scaled packaging (WLCSP) having the capability of the redistributing the electrical circuit is proposed herein to resolve the problem of assembling a fine pitched chip to a coarse pitched substrate. In the fan-out WLCSP, the chip is first attached to a specific 8" chip carrier, and then the trench between the chips are filled by the filler polymer. The solder bumps could be located on both the filler polymer and chip surface, but the fabrication of the fan-out WLCSP is similar to the conventional 8" WLCSP process. Because the packaging structure of the fan-out WLCSP differs from the conventional one, a series of coplanity and solder joint height experiment is conducted to verify the capability of mounting the said structure to the substrate. The experimental results indicated that the derivation of the fan-out WLCSP is approximated plusmn0.01 mm, which is acceptable in the surface mount technology of the substrate. Moreover, the nonlinear finite element (FE) method is applied to analyze the mechanical characteristics of the fan-out WLCSP. Moreover, both the solder joint reliability and the trace stress while the external thermal cycling loading is considered. The simulation result indicates that the distance between the solder joint and the edge of the chip and filler polymer was more sensitive than other the design parameters, and the said distance parameter would dominate the mechanical characteristic of the fan-out WLCSP
{"title":"Design and Analysis of a novel fan-out WLCSP structure","authors":"C. Yuan, G.Q. Zhang, Ching-Shun Huang, Chun-Hui Yu, Chin-Cheng Yang, Wen-Kung Yang, M. Yew, C. Chou, K. Chiang","doi":"10.1109/ESIME.2006.1643970","DOIUrl":"https://doi.org/10.1109/ESIME.2006.1643970","url":null,"abstract":"A novel wafer level chip scaled packaging (WLCSP) having the capability of the redistributing the electrical circuit is proposed herein to resolve the problem of assembling a fine pitched chip to a coarse pitched substrate. In the fan-out WLCSP, the chip is first attached to a specific 8\" chip carrier, and then the trench between the chips are filled by the filler polymer. The solder bumps could be located on both the filler polymer and chip surface, but the fabrication of the fan-out WLCSP is similar to the conventional 8\" WLCSP process. Because the packaging structure of the fan-out WLCSP differs from the conventional one, a series of coplanity and solder joint height experiment is conducted to verify the capability of mounting the said structure to the substrate. The experimental results indicated that the derivation of the fan-out WLCSP is approximated plusmn0.01 mm, which is acceptable in the surface mount technology of the substrate. Moreover, the nonlinear finite element (FE) method is applied to analyze the mechanical characteristics of the fan-out WLCSP. Moreover, both the solder joint reliability and the trace stress while the external thermal cycling loading is considered. The simulation result indicates that the distance between the solder joint and the edge of the chip and filler polymer was more sensitive than other the design parameters, and the said distance parameter would dominate the mechanical characteristic of the fan-out WLCSP","PeriodicalId":60796,"journal":{"name":"微纳电子与智能制造","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2006-04-24","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"79374940","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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