A One-Cycle FIFO Buffer for Memory Management Units in Manycore Systems

Abstract

We present an efficient synchronous first-in first-out (FIFO) buffer for enhanced memory management units and inter-core data communication in manycore systems. Our design significantly reduces hardware overhead and eliminates latency delays by using both the rising and falling clock edges during read and write, which makes our design suitable for increased processing element (PE) utilization by increasing the memory bandwidth in complex network and system on-chip solutions. Compared to prior work, our design can operate 5X faster at the same supply voltage, or up to 44X faster with a 2.5X increase in supply voltage. Our design's total power consumption is 7.8 mW with a total transistor count of 34,470.