Effects of Thermal Annealing on La2O3 Gate Dielectric of InGaZnO Thin-Film Transistor

Abstract

The effects of thermal annealing on La2O3 gate dielectric of InGaZnO thin-film transistor (TFT) are investigated by varying annealing temperature. Due to densification and enhanced moisture resistance of the La2O3 film, its surface roughness and interface with InGaZnO are improved by the thermal annealing, thus leading to significant improvement in the TFT electrical performance. However, higher-temperature (450 C) annealing deteriorates the dielectric roughness and induces more traps associated with grain boundaries in the La2O3 film. The TFT with an appropriate annealing (350 C) shows the best performance with smallest sub-threshold swing (0.276 V/dec), lowest threshold voltage (3.01 V), highest field-effect mobility (23.2 cm/V.s) and largest on-off current ratio (3.52×10). a) Electronic mail: eexdhuang@gmail.com, laip@eee.hku.hk Compared with conventional Si-based thin-film transistors (TFT), InGaZnO TFTs have advantages including low processing temperature, high field-effect mobility as well as good uniformity, and thus have received intensive attention over the last decade. 1 Recently, high-k dielectrics, such as Ta2O5, HfO2, ZrO2, AlZrO and Lu2O3, have been widely investigated to replace SiO2 or Si3N4 as gate dielectrics in InGaZnO TFTs for improving their driving ability and reducing their operating voltage and power consumption. 2-6 Among various high-k materials, La2O3 displays high dielectric constant (~ 30), large band gap (~ 6.0 eV) and good thermodynamic stability with InGaZnO, and thus should be a promising candidate as the gate dielectrics of InGaZnO TFTs. 7,8 It has been demonstrated that Ta incorporated in La2O3 (LaTaO) can further improve the TFT performance by suppressing moisture absorption of the La2O3 film; however, the TFT performance is quite sensitive to Ta content in the LaTaO film, thus leading to uniformity issues. 8 It must be noted that not only the dielectric itself but also the thermal treatment plays a key role in the device performance. Therefore, this work aims to study the thermal and electrical characteristics of InGaZnO TFTs with La2O3 gate dielectric prepared at different annealing temperatures. TFT devices with bottom-gate top-contact configuration were fabricated on heavily p-type Si substrate. The substrate was cleaned by a standard RCA cleaning: firstly, the substrate was submerged in solution I (H2O:H2O2:NH4OH=5:1:1) at 80 C for 10 min to remove organics and particles; then, the substrate was cleaned in solution II (H2O:H2O2:HCl=5:1:1) at 80 C for 10 min to remove metallic contaminants; finally, the substrate was dipped in 2% hydrofluoric acid for 1 min to remove native oxide. After the cleaning, 40-nm La2O3 was deposited on the substrate by radio-frequency sputterer using a La2O3 target in an Ar/O2 ambient. Then, the samples were divided into four groups: two of the groups went through post-deposition annealing (PDA) in N2 at 350 C and 450 C for 10 min respectively, denoted as LaO_350 and LaO_450 samples; the third and fourth groups did not receive PDA,denoted as the as_deposited and control samples respectively. Following that, a 60-nm IGZO active layer was deposited by sputterer using an InGaZnO target in an Ar/O2 ambient. Then, source/drain (S/D) electrodes consisting of 20-nm Ti/80-nm Au were formed by electron-beam evaporation combined with lift-off technique, where Ti was used to enhance the electrode adhesion and also reduce the barrier height between the electrodes and InGaZnO. The channel width (W) and length (L) were 100 μm and 20 μm respectively. Finally, the LaO_350, LaO_450 and control samples received a post-metallization annealing (PMA) in forming gas (H2/O2=5%/95%) at 350 C for 20 min to improve the electrical contacts. The samples with different annealing conditions are summarized in Table 1. Fig. 1 shows the X-ray diffraction (XRD) patterns of the samples with various annealing conditions measured under theta-theta mode, where all the samples display a polycrystalline structure and consists of La2O3 and La(OH)3 in the La2O3 film. La(OH)3 is formed by the reaction of La2O3 with moisture due to the hydroscopic nature of La2O3. 8 For the LaO_350 and LaO_450 samples, the peak (3 1 1) of La(OH)3 decreases significantly relative to that of the sample with no PDA, indicating suppressed formation of La(OH)3 and thus enhanced moisture resistance of La2O3 by the thermal annealing. In addition, compared with the LaO_350 sample, the intense peak (1 1 0) attributed to La2O3 component for the LaO_450 sample exhibits stronger intensity and smaller FWHM (full width at half maximum), indicating more crystallized structure with larger grain size and more grain boundaries induced by the higher-temperature annealing. Moreover, compared with the LaO_350 sample, the more grain boundaries in the LaO_450 one facilitate the diffusion of moisture in the dielectric film, thus enhancing the formation of La(OH)3. Fig. 2 shows the atomic force microscopy (AFM) images of the samples, where the root-mean-square (RMS) roughness is 1.39 nm, 0.90 nm and 1.11 nm for the as_deposited, LaO_350 and LaO_450 samples respectively. Both of the LaO_350 and LaO_450 samples have smoother surface than the as_deposited one because of densification as well as enhanced moisture resistance of the La2O3 film induced by the thermal annealing, which is helpful to suppress the volume expansion of the La2O3 film caused by moisture absorption and thus the formation of La(OH)3. 8 Moreover, the rougher surface of the LaO_450 sample than the LaO_350 one is mainly ascribed to larger grain size induced by the higher-temperature annealing. Fig. 3 shows the transfer characteristics of the devices. The sub-threshold swing SS, saturation carrier mobility μsat, threshold voltage Vth, on-current Ion (defined as ID at VG = 10 V and VD = 5 V) and on-off current ratio Ion/Ioff of the devices are extracted from Fig. 3 and summarized in Table 2. In terms of the parameters listed in Table 2, the control sample shows better performance than the as_deposited one mainly due to the improved electrical contacts and InGaZnO film by PMA. Moreover, the LaO_350 and LaO_450 samples exhibit much better performance than the control one, suggesting that PDA plays a key role in the device performance. The smaller SS of the LaO_350 and LaO_450 samples (LaO_350 ~ 0.276 V/dec; LaO_450 ~ 0. 411V/dec) than the control one (~ 2.11 V/dec) suggests fewer interface states at the dielectric/semiconductor interface, demonstrating that the thermal annealing can effectively improve the interface quality by densifying the dielectric film and improving the interface roughness. Additionally, for the LaO_350 and LaO_450 samples, the better dielectric /semiconductor interface with fewer interface states can suppress the trapping of charge carriers and the trap-related scattering of charge carriers in the conduction channel, thus resulting in lower Vth (LaO_350 ~ 3.01 V; LaO_450 ~ 4.01 V; control ~ 5.00 V) and higher μsat (LaO_350 ~ 23.2 cm/V.s; LaO_450 ~ 5.63 cm/V.s; control ~ 2.11 cm/V.s) than the control one. Moreover, it is known that the by-product La(OH)3 formed by the reaction of La2O3 with moisture increases the negative charge in the dielectric film due to OH replacing O. 9 This increased negative charge density in the dielectric film screens the electric field from the gate, and thus larger gate voltage is required to induce a conduction channel; also, the increased charge density can induce Coulombic scattering on the charge carriers, thus degrading μsat. Consequently, the suppressed formation of La(OH)3 for the LaO_350 and LaO_450 samples further contributes to their lower Vth and higher μsat. Owing to the lower Vth and higher μsat, the LaO_350 and LaO_450 samples achieve much higher Ion (LaO_350 ~ 495 μA; LaO_450 ~ 118 μA) than that of the control one (~ 24.7 μA). Moreover, the higher Ion and suppressed off-state leakage path by thermal annealing of the LaO_350 and LaO_450 samples lead to higher Ion/Ioff ratio (LaO_350 ~ 3.52×10; LaO_450 ~ 4.29×10) than the control one (~ 1.72×10). The control sample displays much larger current under negative VG than the other samples. For the control sample, the PMA would lead to Ti diffusion in the gate dielectric film, thus degrading the quality of the dielectric film and resulting in large leakage current under negative VG. 10 The as_deposited sample did not receive PMA, thus leading to smaller leakage under negative VG than the control one. Although the LaO_350 and LaO_450 samples received the same PMA as the control one, the PDA before the PMA could densify the dielectric film, thus suppressing the Ti diffusion in the dielectric film. Therefore, they also have smaller leakage than the control one. The above analysis needs to be further confirmed. Compared with the LaO_350 sample, the LaO_450 one with higher annealing temperature displays worse performance mainly due to larger grains formed in the dielectric at higher annealing temperature, resulting in more traps along the grain boundaries as well as degraded dielectric/semiconductor interface associated with rougher dielectric film (shown in AFM results in Fig. 2). 7 Therefore, it is believed that the superior performance of the LaO_350 sample is mainly ascribed to the high quality of both the dielectric bulk itself and its interface with the semiconductor achieved by appropriate annealing temperature. Moreover, the LaO_350 sample displays similar μsat (~ 23.2 cm/V.s) as that (~ 23.4 cm/V.s) of the TFT with LaTaO gate dielectric, but much higher Ion/Ioff ratio (~ 3.52×10) than the latter (~ 2.60×10), demonstrating that the appropriate annealing is an effective way to improve the TFT performance. 8 Fig. 4(a) shows the Vth shift (ΔVth) of the samples as a function of stress time under positive gate-bias stress (PGBS). The Vth of the control sample exhibits a positive shift with increasing stress time. However, the LaO_350 sample displays a positive V