Razor-lite: A side-channel error-detection register for timing-margin recovery in 45nm SOI CMOS

Abstract

Advanced CMOS technologies are highly susceptible to process, voltage, and temperature (PVT) variations due to sub-wavelength lithography and other manufacturing challenges. These variations cause performance uncertainty for which timing margins must be added to guarantee correct operation. Ultimately, this results in lost performance or energy: performance is lost directly through reduced clock frequency, while energy is sacrificed by operating at a higher voltage than necessary to meet non-margined timing requirements.