Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487804
H. Fuketa, M. Nomura, M. Takamiya, T. Sakurai
In order to improve the energy efficiency of logic circuits, reductions in capacitance (C) and power supply voltage (VDD) are required, as energy consumption is proportional to CVDD2. Near-threshold (Vt) operation achieves an energy minimum. Resonant clocking can reduce the effective capacitance of the clock distribution network. In this work, a new resonant clocking scheme enabling power reduction at any clock frequency is proposed and applied to a 0.37V 980kHz near-Vt logic circuit in 40nm CMOS.
{"title":"Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits","authors":"H. Fuketa, M. Nomura, M. Takamiya, T. Sakurai","doi":"10.1109/ISSCC.2013.6487804","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487804","url":null,"abstract":"In order to improve the energy efficiency of logic circuits, reductions in capacitance (C) and power supply voltage (VDD) are required, as energy consumption is proportional to CVDD2. Near-threshold (Vt) operation achieves an energy minimum. Resonant clocking can reduce the effective capacitance of the clock distribution network. In this work, a new resonant clocking scheme enabling power reduction at any clock frequency is proposed and applied to a 0.37V 980kHz near-Vt logic circuit in 40nm CMOS.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75426669","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487675
Pang-Ning Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee
Millimeter-Wave and sub-THz imaging sensors have been demonstrated in CMOS technology recently. Mechanical scanners are still required to capture the whole image, making the systems bulky and costly. The limited resolution of the third-dimension (z-direction) also leads to a vague 3D picture. Other 2D solutions need not only focal lens, but large chip area to accommodate more pixels. This paper presents a 94GHz 3D image radar with electronic scanning. Using a 4TX/4RX beamforming technique and a modulated time-of-flight (ToF) algorithm, this prototype achieves ±28° scanning range, 2m maximum distance, and 1mm depth resolution with 960mW of power.
{"title":"A 94GHz 3D-image radar engine with 4TX/4RX beamforming scan technique in 65nm CMOS","authors":"Pang-Ning Chen, Pen-Jui Peng, Chiro Kao, Yu-Lun Chen, Jri Lee","doi":"10.1109/ISSCC.2013.6487675","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487675","url":null,"abstract":"Millimeter-Wave and sub-THz imaging sensors have been demonstrated in CMOS technology recently. Mechanical scanners are still required to capture the whole image, making the systems bulky and costly. The limited resolution of the third-dimension (z-direction) also leads to a vague 3D picture. Other 2D solutions need not only focal lens, but large chip area to accommodate more pixels. This paper presents a 94GHz 3D image radar with electronic scanning. Using a 4TX/4RX beamforming technique and a modulated time-of-flight (ToF) algorithm, this prototype achieves ±28° scanning range, 2m maximum distance, and 1mm depth resolution with 960mW of power.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75605932","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487700
Hyunwoo Cho, U. Ha, Taehwan Roh, Dongchurl Kim, Jeahyuck Lee, Y. Oh, H. Yoo
Recently, short distance board-to-board interconnections are widely employed in portable systems and wearable devices to accommodate many components into an extremely tight footprint. In particular, portable devices such as smart phone and tablet require over 1Gb/s data transfer through ~1mm distance between AP board and a high resolution wide screen display board. Most of display interfaces are implemented with wire-line F-PCB connector, but, they suffer from: 1) high manufacturing cost, 2) the large form factor of the connector and standard socket and 3) large capacitance values of the connector and socket degrading the channel characteristics. So far, various communication interfaces have been tried to realize low cost, small form factor and low energy operation, but with limited success. The bi-phase pule modulation was used in board-to-board communication rather than base-band transmission due to its low energy operation [1-5]. This method used the positive pulse current for data `1' and the negative pulse current for data `0', and the receiver recovered the data by sampling the data at the exact time, which requires an accurate delay control unit. However, the bi-phase pulse modulation consumes significant power because: 1) current pulses sampled at every data consume large current in TX, and 2) a power hungry delay control unit is required to exactly control the sampling time.
{"title":"1.2Gb/s 3.9pJ/b mono-phase pulse-modulation inductive-coupling transceiver for mm-range board-to-board communication","authors":"Hyunwoo Cho, U. Ha, Taehwan Roh, Dongchurl Kim, Jeahyuck Lee, Y. Oh, H. Yoo","doi":"10.1109/ISSCC.2013.6487700","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487700","url":null,"abstract":"Recently, short distance board-to-board interconnections are widely employed in portable systems and wearable devices to accommodate many components into an extremely tight footprint. In particular, portable devices such as smart phone and tablet require over 1Gb/s data transfer through ~1mm distance between AP board and a high resolution wide screen display board. Most of display interfaces are implemented with wire-line F-PCB connector, but, they suffer from: 1) high manufacturing cost, 2) the large form factor of the connector and standard socket and 3) large capacitance values of the connector and socket degrading the channel characteristics. So far, various communication interfaces have been tried to realize low cost, small form factor and low energy operation, but with limited success. The bi-phase pule modulation was used in board-to-board communication rather than base-band transmission due to its low energy operation [1-5]. This method used the positive pulse current for data `1' and the negative pulse current for data `0', and the receiver recovered the data by sampling the data at the exact time, which requires an accurate delay control unit. However, the bi-phase pulse modulation consumes significant power because: 1) current pulses sampled at every data consume large current in TX, and 2) a power hungry delay control unit is required to exactly control the sampling time.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75764277","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487726
Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, L. Kim
Technology scaling and many-core design trends demand detailed information regarding the spatial temperature distribution, which is essential for dynamic thermal management [1,2]. The number of on-chip temperature sensors in high-performance processors is increasing, with state-of-the-art commercial processors embedding up to 44 on-chip sensors [3] and the number is likely to increase in the future (Fig. 14.7.1(a)). We observe two significant challenges in on-chip temperature sensing: 1) the increasing number of sensors, and 2) placing them in a regular manner (not solely on the potential hotspots). The number of sensors is mostly constrained by their area. Indeed, the sensor area is difficult to shrink since large delay lines or a BJT with a large ADC, and digital circuits are required to generate a proportional-to-absolute-temperature (PTAT) signal [2,5,6]. Many-core processor architectures give rise to the second challenge, namely, the hotspot locations within many-core processors are difficult to predict since we cannot determine the task allocation (and heat) profile at design time [2]. Consequently, an area-efficient dense thermal monitoring technique is desirable for next-generation processors.
{"title":"All-digital hybrid temperature sensor network for dense thermal monitoring","authors":"Seungwook Paek, Wongyu Shin, Jaeyoung Lee, Hyo-Eun Kim, Jun-Seok Park, L. Kim","doi":"10.1109/ISSCC.2013.6487726","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487726","url":null,"abstract":"Technology scaling and many-core design trends demand detailed information regarding the spatial temperature distribution, which is essential for dynamic thermal management [1,2]. The number of on-chip temperature sensors in high-performance processors is increasing, with state-of-the-art commercial processors embedding up to 44 on-chip sensors [3] and the number is likely to increase in the future (Fig. 14.7.1(a)). We observe two significant challenges in on-chip temperature sensing: 1) the increasing number of sensors, and 2) placing them in a regular manner (not solely on the potential hotspots). The number of sensors is mostly constrained by their area. Indeed, the sensor area is difficult to shrink since large delay lines or a BJT with a large ADC, and digital circuits are required to generate a proportional-to-absolute-temperature (PTAT) signal [2,5,6]. Many-core processor architectures give rise to the second challenge, namely, the hotspot locations within many-core processors are difficult to predict since we cannot determine the task allocation (and heat) profile at design time [2]. Consequently, an area-efficient dense thermal monitoring technique is desirable for next-generation processors.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"74433434","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487721
Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, D. Jeong
A pixel clock generator is widely utilized in the analog front-ends of digital TVs and also in other video applications. A low integrated jitter is required for good display quality. However, an extremely low input frequency coming from the horizontal synchronization signal (HSYNC) makes it difficult to achieve good jitter performance, because noise from the VCO cannot be sufficiently removed due to the limited loop bandwidth. In this work, a dual-loop architecture is adopted to reduce the phase noise from the VCO based on a ring oscillator. Prior work [1] proposed a dual-loop hybrid PLL composed of an analog loop for the DCO and the digital main loop. Unlike the hybrid architecture [1], our proposed PLL is composed of purely digital components and is synthesized in 28nm CMOS, including the TDC and the DCO, using a cell-based design methodology and automated layout synthesis.
{"title":"A 0.032mm2 3.1mW synthesized pixel clock generator with 30psrms integrated jitter and 10-to-630MHz DCO tuning range","authors":"Wooseok Kim, Jaejin Park, Jihyun F. Kim, Taeik Kim, Hojin Park, D. Jeong","doi":"10.1109/ISSCC.2013.6487721","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487721","url":null,"abstract":"A pixel clock generator is widely utilized in the analog front-ends of digital TVs and also in other video applications. A low integrated jitter is required for good display quality. However, an extremely low input frequency coming from the horizontal synchronization signal (HSYNC) makes it difficult to achieve good jitter performance, because noise from the VCO cannot be sufficiently removed due to the limited loop bandwidth. In this work, a dual-loop architecture is adopted to reduce the phase noise from the VCO based on a ring oscillator. Prior work [1] proposed a dual-loop hybrid PLL composed of an analog loop for the DCO and the digital main loop. Unlike the hybrid architecture [1], our proposed PLL is composed of purely digital components and is synthesized in 28nm CMOS, including the TDC and the DCO, using a cell-based design methodology and automated layout synthesis.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"73576894","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487776
D. El-Damak, Saurav Bandyopadhyay, A. Chandrakasan
Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection.
{"title":"A 93% efficiency reconfigurable switched-capacitor DC-DC converter using on-chip ferroelectric capacitors","authors":"D. El-Damak, Saurav Bandyopadhyay, A. Chandrakasan","doi":"10.1109/ISSCC.2013.6487776","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487776","url":null,"abstract":"Dynamic Voltage Scaling (DVS) has become one of the standard techniques for energy efficient operation of systems by powering circuit blocks at the minimum voltage that meets the desired performance [1]. Switched Capacitor (SC) DC-DC converters have gained significant interest as a promising candidate for an integrated energy conversion solution that eliminates the need for inductors [2,3]. However, SC converters efficiency is limited by the conduction loss, bottom plate parasitic capacitance, gate drive loss in addition to the overhead of the control circuit. Reconfigurable SC converters supporting multi-gain settings have been proposed to allow efficient operation across wide output range [2,4]. Also, High density deep trench capacitors with low bottom plate parasitic capacitance have been utilized in [5] achieving a peak efficiency of 90%. In this work, we exploit on-chip ferroelectric capacitors (Fe-Caps) for charge transfer owing to their high density and extremely low bottom plate parasitic capacitance [6]. High efficiency conversion is achieved by combining the Fe-Caps with multi-gain setting converter in a reconfigurable architecture with dynamic gain selection.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75688456","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487747
Soo-Min Lee, Jong-Hoon Kim, Jongsam Kim, Yunsaing Kim, Hyunbae Lee, J. Sim, Hong-June Park
The transceiver power is reduced by 27% in the single-ended point-to-point DRAM interface by increasing the termination resistance to 4×Z0 at both ends of TX and RX. The resultant increase of ISI and reflection is compensated for at RX by using the 1-tap and 2-tap integrating decision-feedback equalizer (IDFE), respectively, where the reflection tap position and the tap coefficients are found automatically during the training mode. This improves the bathtub opening of a 4-inch FR4 channel from 20% to 62.5% at 5Gb/s in 0.13μm CMOS.
{"title":"A 27% reduction in transceiver power for single-ended point-to-point DRAM interface with the termination resistance of 4×Z0 at both TX and RX","authors":"Soo-Min Lee, Jong-Hoon Kim, Jongsam Kim, Yunsaing Kim, Hyunbae Lee, J. Sim, Hong-June Park","doi":"10.1109/ISSCC.2013.6487747","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487747","url":null,"abstract":"The transceiver power is reduced by 27% in the single-ended point-to-point DRAM interface by increasing the termination resistance to 4×Z0 at both ends of TX and RX. The resultant increase of ISI and reflection is compensated for at RX by using the 1-tap and 2-tap integrating decision-feedback equalizer (IDFE), respectively, where the reflection tap position and the tap coefficients are found automatically during the training mode. This improves the bathtub opening of a 4-inch FR4 channel from 20% to 62.5% at 5Gb/s in 0.13μm CMOS.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77655972","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487623
Yue Lu, E. Alon
Given the continuously climbing data rates of high-speed I/O's, equalizer circuits-and particularly decision-feedback equalizer (DFE) designs-are being pushed to operate at ever-higher speeds. At 20 to 40Gb/s data-rates, loop-unrolled DFEs are widely adopted to relieve the feedback timing constraints of the initial tap(s) [1]. However, loop-unrolling introduces additional delay into the critical paths of later (non-unrolled) DFE taps due to the selection MUXes, and with its exponential growth in complexity, does not scale well as the number of unrolled taps increases. Perhaps due to this challenge, no multi-tap DFE solutions with single pJ/bit efficiencies have yet been demonstrated at data rates >40Gb/s.
{"title":"A 66Gb/s 46mW 3-tap decision-feedback equalizer in 65nm CMOS","authors":"Yue Lu, E. Alon","doi":"10.1109/ISSCC.2013.6487623","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487623","url":null,"abstract":"Given the continuously climbing data rates of high-speed I/O's, equalizer circuits-and particularly decision-feedback equalizer (DFE) designs-are being pushed to operate at ever-higher speeds. At 20 to 40Gb/s data-rates, loop-unrolled DFEs are widely adopted to relieve the feedback timing constraints of the initial tap(s) [1]. However, loop-unrolling introduces additional delay into the critical paths of later (non-unrolled) DFE taps due to the selection MUXes, and with its exponential growth in complexity, does not scale well as the number of unrolled taps increases. Perhaps due to this challenge, no multi-tap DFE solutions with single pJ/bit efficiencies have yet been demonstrated at data rates >40Gb/s.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80261321","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487758
Chun-Geik Tan, Fei Song, Tieng Yi Choke, Ming Kong, De-Cheng Song, C. Yong, W. Shu, Z. You, Yi-Hsien Lin, O. Shana'a
Global Navigation Satellite Systems (GNSS) have a spectrum allocation shown in Fig. 19.4.1. The time-to-first-lock and location accuracy can be improved through simultaneous reception of two different satellite signals. This usually necessitates the use of two dedicated receivers [1] driven by a single and sometimes two separate synthesizers, which increases complexity, die area, and most importantly current consumption. To solve this problem, the architecture shown in Fig. 19.4.1 is proposed. The SoC consists of one single reconfigurable low-IF receiver, a single fractional-N frequency synthesizer, and a digital baseband processor. Since different satellite signals are uncorrelated and are buried well below the noise floor, they can be amplified and downconverted by the same RF/analog chain as an image of one another, and then separated in the digital domain by the corresponding correlator and signal processor. In the case of simultaneous GPS/Galileo and Glonass dual reception, the LO (fLO_GG) is set to 1588.608MHz. As a result, the GPS/Galileo signal becomes the image of the Glonass satellite signal with an IF frequency of 13.1MHz. Similarly, when the LO (fLO_GB) is set to 1568.256MHz, the resulting IF frequency is about 7.1MHz for GPS/Galileo and Beidou dual reception. For GPS/Galileo-only reception, the LO (fLO_GPS) is set to 1571.328MHz resulting in an IF frequency of 4.092MHz.
{"title":"A universal GNSS (GPS/Galileo/Glonass/Beidou) SoC with a 0.25mm2 radio in 40nm CMOS","authors":"Chun-Geik Tan, Fei Song, Tieng Yi Choke, Ming Kong, De-Cheng Song, C. Yong, W. Shu, Z. You, Yi-Hsien Lin, O. Shana'a","doi":"10.1109/ISSCC.2013.6487758","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487758","url":null,"abstract":"Global Navigation Satellite Systems (GNSS) have a spectrum allocation shown in Fig. 19.4.1. The time-to-first-lock and location accuracy can be improved through simultaneous reception of two different satellite signals. This usually necessitates the use of two dedicated receivers [1] driven by a single and sometimes two separate synthesizers, which increases complexity, die area, and most importantly current consumption. To solve this problem, the architecture shown in Fig. 19.4.1 is proposed. The SoC consists of one single reconfigurable low-IF receiver, a single fractional-N frequency synthesizer, and a digital baseband processor. Since different satellite signals are uncorrelated and are buried well below the noise floor, they can be amplified and downconverted by the same RF/analog chain as an image of one another, and then separated in the digital domain by the corresponding correlator and signal processor. In the case of simultaneous GPS/Galileo and Glonass dual reception, the LO (fLO_GG) is set to 1588.608MHz. As a result, the GPS/Galileo signal becomes the image of the Glonass satellite signal with an IF frequency of 13.1MHz. Similarly, when the LO (fLO_GB) is set to 1568.256MHz, the resulting IF frequency is about 7.1MHz for GPS/Galileo and Beidou dual reception. For GPS/Galileo-only reception, the LO (fLO_GPS) is set to 1571.328MHz resulting in an IF frequency of 4.092MHz.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80402333","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2013-03-28DOI: 10.1109/ISSCC.2013.6487704
T. Kono, T. Ito, T. Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Y. Kawashima, H. Hidaka, T. Yamauchi
This paper presents 40nm eFlash macros for automotive. There are three key features; 1) a 40nm SG-MONOS cell scaled to the next generation of [1]; 2) a fast random-read-access (over 160MHz) and the developed sense amplifier (SA); and, 3) circuit techniques for reliable and fast P/E operations even at the junction temperature (Tj) of 170°C.
{"title":"40nm embedded SG-MONOS flash macros for automotive with 160MHz random access for code and endurance over 10M cycles for data","authors":"T. Kono, T. Ito, T. Tsuruda, Takayuki Nishiyama, Tsutomu Nagasawa, Tomoya Ogawa, Y. Kawashima, H. Hidaka, T. Yamauchi","doi":"10.1109/ISSCC.2013.6487704","DOIUrl":"https://doi.org/10.1109/ISSCC.2013.6487704","url":null,"abstract":"This paper presents 40nm eFlash macros for automotive. There are three key features; 1) a 40nm SG-MONOS cell scaled to the next generation of [1]; 2) a fast random-read-access (over 160MHz) and the developed sense amplifier (SA); and, 3) circuit techniques for reliable and fast P/E operations even at the junction temperature (Tj) of 170°C.","PeriodicalId":6378,"journal":{"name":"2013 IEEE International Solid-State Circuits Conference Digest of Technical Papers","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2013-03-28","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77079749","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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