{"title":"Realization of a 1.5 bits/stage pipeline ADC using switched capacitor technique","authors":"Pranati Ghoshal, S. Sen","doi":"10.1109/ICICPI.2016.7859675","DOIUrl":null,"url":null,"abstract":"Various types of ADCs are available in the market with their relative strengths and constraints. Pipeline ADC is the latest inclusion in this list. It is very high speed and high resolution in nature. To make the conversion error free, a digital error correction technique has been used which is termed as 1.5 bits/stage. This design is a very useful technique to eliminate error due to comparator offset. The architecture is so designed that it does not need any extra circuitry for error detection and correction. To realize 4 bits from 4 stages, 1.5 bits/stage technique is used and error curves are drawn between theoretical and practical values which shows close proximity between them.","PeriodicalId":6501,"journal":{"name":"2016 International Conference on Intelligent Control Power and Instrumentation (ICICPI)","volume":"2 1","pages":"65-66"},"PeriodicalIF":0.0000,"publicationDate":"2016-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"3","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 International Conference on Intelligent Control Power and Instrumentation (ICICPI)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICICPI.2016.7859675","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 3
Abstract
Various types of ADCs are available in the market with their relative strengths and constraints. Pipeline ADC is the latest inclusion in this list. It is very high speed and high resolution in nature. To make the conversion error free, a digital error correction technique has been used which is termed as 1.5 bits/stage. This design is a very useful technique to eliminate error due to comparator offset. The architecture is so designed that it does not need any extra circuitry for error detection and correction. To realize 4 bits from 4 stages, 1.5 bits/stage technique is used and error curves are drawn between theoretical and practical values which shows close proximity between them.
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