Low-Voltage Low-Power Sub-Threshold CMOS Four-Quadrant Analogue Multiplier

Abstract

A four-quadrant analogue multiplier with low-voltage low-power is proposed in this paper. The design techniques are based on sub-threshold CMOS voltage amplifier and the voltage-sum circuit. The circuit can operate for two input voltages range of $\pmb{\pm 25}\ \mathbf{mV}$, with the harmonic distortion is 1.3%. Furthermore, its features are 0.8 V power supply, $\pmb{0.78 \mu}\ \mathbf{W}$ power consumption, and 650 kHz bandwidth. The proposed circuit is designed using standard $\pmb{0.18 \mu}\ \mathbf{m}$ CMOS technology. The SPICE simulation results show the performance of the circuit and confirm the validity of the design technique.