Design of a 2.5-GHz, 3-ps jitter, 8-locking-cycle, all-digital delay-locked loop with cycle-by-cycle phase adjustment

Abstract

This paper describes the design of a multi-GHz ADDLL. HDSC-based coarse-fine architecture is adopted to achieve low power and to avoid harmonic locking at large operating frequency ranges. A new resettable coarse delay line and an asynchronous binary-search design are proposed to achieve fast coarse locking and fine locking, respectively. A novel maintenance operation is also proposed to allow phase adjustments to be performed during each cycle to effectively suppress the jitter. The measurement results show that the designed 1.0-V, 55-nm ADDLL has a peak-to-peak jitter of 3 ps and a locking time of 8 cycles when operated at 2.5 GHz with a power dissipation of only 1.96 mW.