Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243780
X. Xue, Wenxiang Jian, Jianguo Yang, F. Xiao, Gang Chen, X. L. Xu, Yufeng Xie, Yinyin Lin, R. Huang, Qingtian Zhou, Jingang Wu
A 0.13μm 8Mb CuxSiyO resistive memory test macro with 20F2 cell size is developed based on logic process for the first time. Smart and adaptive assist write and read circuit are proposed and verified in order to fix yield and power consumption issues from large write speed and high temperature resistance variation. SAWM (self-adaptive write mode) helps to enlarge Roff/Ron window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and large power consumption is eliminated after set success. SARM (Self-adaptive read mode) improves read bit yield from 98% to 100% at 125°C. The typical access time of on-pitch voltage sensing SA(sense amplifier) is 21ns and high bandwidth throughput is supported.
{"title":"A 0.13µm 8Mb logic based CuxSiyO resistive memory with self-adaptive yield enhancement and operation power reduction","authors":"X. Xue, Wenxiang Jian, Jianguo Yang, F. Xiao, Gang Chen, X. L. Xu, Yufeng Xie, Yinyin Lin, R. Huang, Qingtian Zhou, Jingang Wu","doi":"10.1109/VLSIC.2012.6243780","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243780","url":null,"abstract":"A 0.13μm 8Mb CuxSiyO resistive memory test macro with 20F2 cell size is developed based on logic process for the first time. Smart and adaptive assist write and read circuit are proposed and verified in order to fix yield and power consumption issues from large write speed and high temperature resistance variation. SAWM (self-adaptive write mode) helps to enlarge Roff/Ron window from 8X to 24X at room temperature. The reset bit yield is improved from 61.5% to 100% and large power consumption is eliminated after set success. SARM (Self-adaptive read mode) improves read bit yield from 98% to 100% at 125°C. The typical access time of on-pitch voltage sensing SA(sense amplifier) is 21ns and high bandwidth throughput is supported.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75826392","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243860
Inhee Lee, S. Bang, Yoonmyung Lee, Yejoong Kim, Gyouho Kim, D. Sylvester, D. Blaauw
We propose a low power battery voltage supervisory circuit for micro-scale sensor systems that provides power-on reset, brown-out detection, and recovery detection to prevent malfunction and battery damage. Ultra-low power is achieved using a 57 pA, fast stabilizing two-stage voltage reference and an 81 pA leakage-based oscillator and clocked comparator. The supervisor was fabricated in 180 nm CMOS and integrated with a complete 1 mm3 sensor system. It consumes 635 pW at 3.6 V supply voltage, which is an 850× reduction over the best prior work.
{"title":"A 635pW battery voltage supervisory circuit for miniature sensor nodes","authors":"Inhee Lee, S. Bang, Yoonmyung Lee, Yejoong Kim, Gyouho Kim, D. Sylvester, D. Blaauw","doi":"10.1109/VLSIC.2012.6243860","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243860","url":null,"abstract":"We propose a low power battery voltage supervisory circuit for micro-scale sensor systems that provides power-on reset, brown-out detection, and recovery detection to prevent malfunction and battery damage. Ultra-low power is achieved using a 57 pA, fast stabilizing two-stage voltage reference and an 81 pA leakage-based oscillator and clocked comparator. The supervisor was fabricated in 180 nm CMOS and integrated with a complete 1 mm3 sensor system. It consumes 635 pW at 3.6 V supply voltage, which is an 850× reduction over the best prior work.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"72956706","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243794
Hyo-Gyuem Rhew, J. Jeong, Jeffrey Fredenburg, Sunjay Dodani, Parag G. Patil, M. Flynn
A log-based closed-loop Deep Brain Stimulation system detects and processes low-frequency brain field signals to optimize stimulation parameters. The fully self-contained single-chip system incorporates LNAs, a log-ADC, digital log-filters, a log-DSP with a PI-controller, current stimulators, a two-way wireless transceiver, a clock generator, and an RF energy harvester. The 2×2mm2 180nm CMOS prototype consumes 468μW for recording and processing neural signals, stimulation, and for two-way wireless communication.
{"title":"A wirelessly powered log-based closed-loop deep brain stimulation SoC with two-way wireless telemetry for treatment of neurological disorders","authors":"Hyo-Gyuem Rhew, J. Jeong, Jeffrey Fredenburg, Sunjay Dodani, Parag G. Patil, M. Flynn","doi":"10.1109/VLSIC.2012.6243794","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243794","url":null,"abstract":"A log-based closed-loop Deep Brain Stimulation system detects and processes low-frequency brain field signals to optimize stimulation parameters. The fully self-contained single-chip system incorporates LNAs, a log-ADC, digital log-filters, a log-DSP with a PI-controller, current stimulators, a two-way wireless transceiver, a clock generator, and an RF energy harvester. The 2×2mm2 180nm CMOS prototype consumes 468μW for recording and processing neural signals, stimulation, and for two-way wireless communication.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"80230173","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243775
B. Hershberg, S. Weaver, Kazuki Sobue, S. Takeuchi, K. Hamashita, U. Moon
A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18μm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.
{"title":"A 61.5dB SNDR pipelined ADC using simple highly-scalable ring amplifiers","authors":"B. Hershberg, S. Weaver, Kazuki Sobue, S. Takeuchi, K. Hamashita, U. Moon","doi":"10.1109/VLSIC.2012.6243775","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243775","url":null,"abstract":"A ring amplifier based pipelined ADC is presented that uses simple cells constructed from small inverters and capacitors to perform amplification. The basic ring amplifier structure is characterized and demonstrated to be highly scalable, power efficient, and compression-immune (inherent rail-to-rail output swing). The prototype 10.5-bit ADC, fabricated in 0.18μm CMOS technology, achieves 61.5dB SNDR at a 30MHz sampling rate and consumes 2.6mW, resulting in a FoM of 90fJ/conversion-step.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83102032","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243801
D. Stepanovic, B. Nikolić
This paper presents a power- and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMOS. At 2.8GS/s sampling rate the ADC consumes 44.6mW of power from a 1.2V supply while achieving peak SNDR of 50.9dB and retaining SNDR higher than 48.2dB across the entire first Nyquist zone.
{"title":"A 2.8GS/s 44.6mW time-interleaved ADC achieving 50.9dB SNDR and 3dB effective resolution bandwidth of 1.5GHz in 65nm CMOS","authors":"D. Stepanovic, B. Nikolić","doi":"10.1109/VLSIC.2012.6243801","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243801","url":null,"abstract":"This paper presents a power- and area-efficient 24-way time-interleaved SAR ADC designed in 65nm CMOS. At 2.8GS/s sampling rate the ADC consumes 44.6mW of power from a 1.2V supply while achieving peak SNDR of 50.9dB and retaining SNDR higher than 48.2dB across the entire first Nyquist zone.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"83118347","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm2. This chip drains 24mW from a 1.2V power supply.
{"title":"A 160-GHz receiver-based phase-locked loop in 65 nm CMOS technology","authors":"Wei-Zen Chen, Tai-You Lu, Yan-Ting Wang, Jhong-Ting Jian, Yi-Hung Yang, G. Huang, Wen-De Liu, Chih-Hua Hsiao, Shu-Yu Lin, Jung-Yen Liao","doi":"10.1109/VLSIC.2012.6243765","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243765","url":null,"abstract":"A 160-GHz receiver-based PLL with tuning range from 156.4 GHz to 159.2 GHz is presented. Sub-THz 1/9 prescaler is replaced by a 3rd harmonic mixer incorporating frequency tripler for frequency down conversion. Frequency acquisition is assisted by received signal strength indicator (RSSI) for automatically frequency sweeping and fast locking. The frequency locking time is less than 3 μsec. Fabricated in 65 nm CMOS technology, the chip size is 0.92mm2. This chip drains 24mW from a 1.2V power supply.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84674331","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243787
A. Arbabian, Shinwon Kang, Steven Callender, Jun-Chau Chien, B. Afshar, A. Niknejad
An integrated phase-coherent and pixel-scalable pulsed-radar transceiver with on-chip tapered loop antennas generates programmable pulses down to 36ps using an integrated 94GHz carrier, frequency synthesized and locked to an external reference. A DLL controls the TX pulse position with 2.28ps resolution, which allows the chip to function as a unit element in a timed-array. The receiver also features a >;1.5THz GBW DA as the front-end amplifier, quadrature mixers, and a 26GHz quadrature baseband. Phase coherency allows for ~375μm single-target position resolution by interferometry.
{"title":"A 94GHz mm-wave to baseband pulsed-radar for imaging and gesture recognition","authors":"A. Arbabian, Shinwon Kang, Steven Callender, Jun-Chau Chien, B. Afshar, A. Niknejad","doi":"10.1109/VLSIC.2012.6243787","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243787","url":null,"abstract":"An integrated phase-coherent and pixel-scalable pulsed-radar transceiver with on-chip tapered loop antennas generates programmable pulses down to 36ps using an integrated 94GHz carrier, frequency synthesized and locked to an external reference. A DLL controls the TX pulse position with 2.28ps resolution, which allows the chip to function as a unit element in a timed-array. The receiver also features a >;1.5THz GBW DA as the front-end amplifier, quadrature mixers, and a 26GHz quadrature baseband. Phase coherency allows for ~375μm single-target position resolution by interferometry.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"77874542","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243772
Yun-Shiang Shu
A 6b 3GS/s fully dynamic flash ADC is fabricated in 40nm CMOS and occupies 0.021mm2. Dynamic comparators with digitally controlled built-in offset are realized with imbalanced tails. Half of the comparators are substituted with simple SR latches. The ADC achieves SNDRs of 36.2dB and 33.1dB at DC and Nyquist, respectively, while consuming 11mW from a 1.1V supply.
{"title":"A 6b 3GS/s 11mW fully dynamic flash ADC in 40nm CMOS with reduced number of comparators","authors":"Yun-Shiang Shu","doi":"10.1109/VLSIC.2012.6243772","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243772","url":null,"abstract":"A 6b 3GS/s fully dynamic flash ADC is fabricated in 40nm CMOS and occupies 0.021mm2. Dynamic comparators with digitally controlled built-in offset are realized with imbalanced tails. Half of the comparators are substituted with simple SR latches. The ADC achieves SNDRs of 36.2dB and 33.1dB at DC and Nyquist, respectively, while consuming 11mW from a 1.1V supply.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"75002420","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243838
Tsung-Te Liu, J. Rabaey
A neural signal processor exploits an asynchronous timing strategy to dynamically minimize leakage and to self-adapt to the process variations and different operating conditions. Based on a logic topology with built-in leakage suppression, the self-timed processor demonstrates robust sub-threshold operation down to 0.25V, while consuming only 460nW in 0.03mm2 in a 65nm CMOS technology, representing a 4.4X reduction in power compared to the state-of-the-art designs.
{"title":"A 0.25V 460nW asynchronous neural signal processor with inherent leakage suppression","authors":"Tsung-Te Liu, J. Rabaey","doi":"10.1109/VLSIC.2012.6243838","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243838","url":null,"abstract":"A neural signal processor exploits an asynchronous timing strategy to dynamically minimize leakage and to self-adapt to the process variations and different operating conditions. Based on a logic topology with built-in leakage suppression, the self-timed processor demonstrates robust sub-threshold operation down to 0.25V, while consuming only 460nW in 0.03mm2 in a 65nm CMOS technology, representing a 4.4X reduction in power compared to the state-of-the-art designs.","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"84990422","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
Pub Date : 2012-06-13DOI: 10.1109/VLSIC.2012.6243815
Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, M. Ho, H. Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, H. Yamauchi
This work proposes bit-line (BL) swing expansion schemes (BL-EXPD), which minimize the product (A*VDDmin) of SRAM cell area (A) and the minimum operation voltage (VDDmin) to the best of our knowledge. The key-enablers to minimize A*VDDmin are: L-shaped 7T cell (L7T) and BL-EXPD. The L7T features: (1) an area efficient cell layout, (2) a read-disturb free decoupled 1T read port (RP), and (3) a half-select disturb free write back scheme[1]. The BL-EXPD enables a 9× larger read-BL (RBL) swing at the 6σ point than that in our previously proposed Z8T[2] and allows single BL sensing to reduce cell area. A fabricated 65nm 256-row BL 32Kb L7T SRAM achieved a 260mV VDDmin. As a result, its A*VDDmin is ~50% lower than for Z8T and conventional 8T SRAM cells [3,4].
{"title":"A 260mV L-shaped 7T SRAM with bit-line (BL) Swing expansion schemes based on boosted BL, asymmetric-VTH read-port, and offset cell VDD biasing techniques","authors":"Ming-Pin Chen, Lai-Fu Chen, Meng-Fan Chang, Shu-Meng Yang, Yao-Jen Kuo, Jui-Jen Wu, M. Ho, H. Su, Yuan-Hua Chu, Wen-Chin Wu, Tzu-Yi Yang, H. Yamauchi","doi":"10.1109/VLSIC.2012.6243815","DOIUrl":"https://doi.org/10.1109/VLSIC.2012.6243815","url":null,"abstract":"This work proposes bit-line (BL) swing expansion schemes (BL-EXPD), which minimize the product (A*VDDmin) of SRAM cell area (A) and the minimum operation voltage (VDDmin) to the best of our knowledge. The key-enablers to minimize A*VDDmin are: L-shaped 7T cell (L7T) and BL-EXPD. The L7T features: (1) an area efficient cell layout, (2) a read-disturb free decoupled 1T read port (RP), and (3) a half-select disturb free write back scheme[1]. The BL-EXPD enables a 9× larger read-BL (RBL) swing at the 6σ point than that in our previously proposed Z8T[2] and allows single BL sensing to reduce cell area. A fabricated 65nm 256-row BL 32Kb L7T SRAM achieved a 260mV VDDmin. As a result, its A*VDDmin is ~50% lower than for Z8T and conventional 8T SRAM cells [3,4].","PeriodicalId":6347,"journal":{"name":"2012 Symposium on VLSI Circuits (VLSIC)","volume":null,"pages":null},"PeriodicalIF":0.0,"publicationDate":"2012-06-13","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":null,"resultStr":null,"platform":"Semanticscholar","paperid":"85458761","PeriodicalName":null,"FirstCategoryId":null,"ListUrlMain":null,"RegionNum":0,"RegionCategory":"","ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":"","EPubDate":null,"PubModel":null,"JCR":null,"JCRName":null,"Score":null,"Total":0}
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