{"title":"Cell-library design methodology for integrated RSFQ-logic","authors":"Steffen Lange, Hannes Toepfer, Hermann F. Uhlmann","doi":"10.1016/S0964-1807(99)00022-8","DOIUrl":null,"url":null,"abstract":"<div><p>The application of a systematic design approach to develop integrated superconductive circuits based on the Rapid Single Flux Quantum (RSFQ) principle is described. The methodology is utilized to meet the demands of handling circuits of increasing complexity. For this, we developed design facilities which are based on a low-level basic cell library comprising schematic capture, automated netlist synthesis, and formal verification. The intermediate design results are analyzed using advanced simulation techniques corresponding to the given abstractions level. Cells are described on device level and by their logical behavior as well. So we can execute circuit level simulation, logic level simulation and mixed mode simulation in the same environment. The typical design flow is illustrated with an example taken from the development of a particular RSFQ application.</p></div>","PeriodicalId":100110,"journal":{"name":"Applied Superconductivity","volume":"6 10","pages":"Pages 633-639"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-01","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"https://sci-hub-pdf.com/10.1016/S0964-1807(99)00022-8","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"Applied Superconductivity","FirstCategoryId":"1085","ListUrlMain":"https://www.sciencedirect.com/science/article/pii/S0964180799000228","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
The application of a systematic design approach to develop integrated superconductive circuits based on the Rapid Single Flux Quantum (RSFQ) principle is described. The methodology is utilized to meet the demands of handling circuits of increasing complexity. For this, we developed design facilities which are based on a low-level basic cell library comprising schematic capture, automated netlist synthesis, and formal verification. The intermediate design results are analyzed using advanced simulation techniques corresponding to the given abstractions level. Cells are described on device level and by their logical behavior as well. So we can execute circuit level simulation, logic level simulation and mixed mode simulation in the same environment. The typical design flow is illustrated with an example taken from the development of a particular RSFQ application.