Applied Superconductivity最新文献

We report on high quality planar junctions fabricated from well characterized c-axis quasi-homoepitaxial NdBa₂ Cu₃O_7−δ/PrBa₂Cu₃O_7−δ/NdBa₂Cu₃O_7−δ multilayers. C-axis tunneling spectroscopy investigations provide evidence of quasiparticle tunneling that is commonly observed for superconductor-insulator-superconductor (SIS) junctions. We observed a temperature dependent BCS like gap giving 2Δ/K_BT_c=6. The tunneling conductance dI/dV of the junctions in parallel magnetic field reveals an anomalous splitting of the superconducting quasiparticle density of states. The magnitude of the splitting can be related to the magnetic moment of the quasiparticles.

It is possible to produce HTSC thin films of polymer metal precursors by the simple spincoating technique. This method can be used to manufacture of Y–Ba–Cu–O- and Bi–Sr–Ca–Cu–O–HTSC thin films. The microbridges are generated into the precursor film by photolithography. The etching process step is cancelled. After that the superconducting phases are formed at 950°C respectively 865°C during the tempering process. The HTSC structures serve as a previous stage for SNS contact. The critical temperatures (T_c) measured on the 20 and 200 μm wide microbridges are 82 K for Y–Ba–Cu–O and 108 K for Bi–Sr–Ca–Cu–O. The critical current density (j_c) obtained is 10⁵ A/cm² for 65 K.

We carried out a design study of single electron devices based on submicron metallic islands and tunnel junctions. The results of a first capacitive design analysis using a three-dimensional numerical field computation of separated circuit cells are used as input for an optimization with respect to cross-talk between neighboring circuit cells. We discuss the reduction of parasitic effects by use of additional shielding electrodes on the top of the substrate or in the background. In view of the influenced charge associated with parasitic background charges we discuss the charge distribution on a three-dimensional scan of the substrate below the structures for the study of critical influence regions, where a certain threshold of influenced charge at neighbor electrodes is given. We show that the influence calculation of the parasitic background charge is of significant importance for the design and fabrication of single charge circuits.

The origin of 1/f voltage noise in different types of Josephson junctions fabricated from the high temperature superconductors (HTS) have been traced back to the trapping and release of charge carriers in trapping centers in an insulating barrier giving rise to correlated fluctuations of the junction critical current I_c and normal state resistance R_n. For the normalized fluctuations S_I and S_R a linear scaling with R_n has been observed which suggests an almost constant density of trapping centers for all investigated HTS Josephson junctions. Using this linear scaling we have made an approximate calculation of the density of the trapping centers.

The application of a systematic design approach to develop integrated superconductive circuits based on the Rapid Single Flux Quantum (RSFQ) principle is described. The methodology is utilized to meet the demands of handling circuits of increasing complexity. For this, we developed design facilities which are based on a low-level basic cell library comprising schematic capture, automated netlist synthesis, and formal verification. The intermediate design results are analyzed using advanced simulation techniques corresponding to the given abstractions level. Cells are described on device level and by their logical behavior as well. So we can execute circuit level simulation, logic level simulation and mixed mode simulation in the same environment. The typical design flow is illustrated with an example taken from the development of a particular RSFQ application.

We present results of our experimental investigations of the dynamic properties of two types of shorted two-dimensional (2D) arrays. The first type consisted of 4×4 YBCO step edge junctions integrated into a circuit, which allowed the simultaneous detection of all single row voltages. Thus, using only dc-measurements, the interaction and synchronization between the rows could be observed. In the second investigated array type the edge junctions of the rows were closed into superconducting loops in the form of coplanar resonators. Resonant steps were observed on the current–voltage characteristic due to interaction of the junctions with the resonators. The circuits were integrated into a stripline geometry and coupled to another (detector) Josephson junction. A clear detector response, i.e. Shapiro steps, was measured up to 460 GHz. Steps up to 4th harmonic were observed in the frequency range 150–200 GHz.

A new process for making high-temperature superconducting multilayer circuits is reported in detail. Proximity exposure was used to form controllable shallow edges which are required for the crossovers and interconnects. Small features with shallow edges can be achieved by the combination of contact exposure and proximity exposure. Stacked Josephson junctions on STO bicrystal substrates were prepared using this process and tested. A multilayer low-inductance dc-SQUID fabricated using this process shows large voltage modulation.

We report on the experimental full operation of a processor interface node circuit (an RIF circuit), which is the most important component of our proposed superconducting ring network. This circuit was designed for the prototype three-node ring network system. At over 1 GHz, we successfully operated the packet-validity-checking and validity-setting parts, which include the critical path of the RIF circuit. Our results strongly suggest that GHz-level operation of the RIF circuit is attainable.

We propose a method for inductance calculation of three-dimensional superconducting structures by using software designed for high-frequency normal metal cases. By examining the analytical expressions for the current density distributions of the same ideal parallel plane structure in both the high-frequency normal metal case and the superconductor case, we obtain a correction factor for the kinetic inductance calculation in the latter. It is then assumed that this correction factor can be applied to real superconducting layers with finite widths. The total inductance of any superconducting structure can be obtained by finding the magnetic field energy in the high-frequency normal metal case with the same configuration, and adding the kinetic energy with the correction factor applied. Normal metal field simulators, such as MAXWELL, can readily be used. A SQUID loop inductance is simulated as a test case on MAXWELL, and 3% agreement is achieved with the experimental result.